bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.310s | 1.408ms | 1 | 1 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 26.404s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 1.800s | 636.473us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.230s | 497.821us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 0.920s | 646.000us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 26.404s | 0 | 1 | 0.00 | |
| aon_timer_csr_aliasing | 1.230s | 497.821us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.770s | 404.062us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0.720s | 525.884us | 1 | 1 | 100.00 |
| V1 | TOTAL | 6 | 8 | 75.00 | |||
| V2 | prescaler | aon_timer_prescaler | 0 | 1 | 0.00 | ||
| V2 | jump | aon_timer_jump | 0 | 1 | 0.00 | ||
| V2 | stress_all | aon_timer_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | aon_timer_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | aon_timer_intr_test | 0.770s | 334.203us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 1.720s | 418.798us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 1.720s | 418.798us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.310s | 1.408ms | 1 | 1 | 100.00 |
| aon_timer_csr_rw | 26.404s | 0 | 1 | 0.00 | |||
| aon_timer_csr_aliasing | 1.230s | 497.821us | 1 | 1 | 100.00 | ||
| aon_timer_same_csr_outstanding | 2.770s | 2.143ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.310s | 1.408ms | 1 | 1 | 100.00 |
| aon_timer_csr_rw | 26.404s | 0 | 1 | 0.00 | |||
| aon_timer_csr_aliasing | 1.230s | 497.821us | 1 | 1 | 100.00 | ||
| aon_timer_same_csr_outstanding | 2.770s | 2.143ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 3 | 7 | 42.86 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 0 | 1 | 0.00 | ||
| aon_timer_tl_intg_err | 2.080s | 4.601ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 2.080s | 4.601ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | max_threshold | aon_timer_smoke_max_thold | 0 | 1 | 0.00 | ||
| V3 | min_threshold | aon_timer_smoke_min_thold | 0 | 1 | 0.00 | ||
| V3 | wkup_count_hi_cdc | aon_timer_wkup_count_cdc_hi | 0 | 1 | 0.00 | ||
| V3 | custom_intr | aon_timer_custom_intr | 0 | 1 | 0.00 | ||
| V3 | alternating_on_off | aon_timer_alternating_enable_on_off | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 6 | 0.00 | |||
| TOTAL | 10 | 23 | 43.48 |
Job killed most likely because its dependent job failed. has 12 failures:
Test aon_timer_smoke has 1 failures.
Test aon_timer_prescaler has 1 failures.
Test aon_timer_jump has 1 failures.
Test aon_timer_custom_intr has 1 failures.
Test aon_timer_smoke_max_thold has 1 failures.
... and 7 more tests.
Job returned non-zero exit code has 2 failures:
Test default has 1 failures.
default
Log /nightly/current_run/scratch/master/aon_timer-sim-vcs/default/build.log
recompiling module tb
All of 84 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 18.808 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test aon_timer_csr_rw has 1 failures.
0.aon_timer_csr_rw.93001439383547492449481358126443834661983016495158300857088214262383833131313
Log /nightly/current_run/scratch/master/aon_timer-sim-vcs/0.aon_timer_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 16:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255