EDN Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke			0	1	0.00
V1	csr_hw_reset	edn_csr_hw_reset	0.770s	34.284us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.730s	54.528us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.380s	67.820us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.140s	53.069us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.810s	33.495us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.730s	54.528us	1	1	100.00
		edn_csr_aliasing	1.140s	53.069us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	firmware	edn_genbits			0	1	0.00
V2	csrng_commands	edn_genbits			0	1	0.00
V2	genbits	edn_genbits			0	1	0.00
V2	interrupts	edn_intr			0	1	0.00
V2	alerts	edn_alert			0	1	0.00
V2	errs	edn_err			0	1	0.00
V2	disable	edn_disable			0	1	0.00
		edn_disable_auto_req_mode			0	1	0.00
V2	stress_all	edn_stress_all			0	1	0.00
V2	intr_test	edn_intr_test	0.740s	14.555us	1	1	100.00
V2	alert_test	edn_alert_test			0	1	0.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.740s	519.510us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.740s	519.510us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.770s	34.284us	1	1	100.00
		edn_csr_rw	0.730s	54.528us	1	1	100.00
		edn_csr_aliasing	1.140s	53.069us	1	1	100.00
		edn_same_csr_outstanding	0.790s	49.411us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.770s	34.284us	1	1	100.00
		edn_csr_rw	0.730s	54.528us	1	1	100.00
		edn_csr_aliasing	1.140s	53.069us	1	1	100.00
		edn_same_csr_outstanding	0.790s	49.411us	1	1	100.00
V2		TOTAL			3	11	27.27
V2S	tl_intg_err	edn_sec_cm			0	1	0.00
		edn_tl_intg_err	1.860s	314.493us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen			0	1	0.00
V2S	sec_cm_config_mubi	edn_alert			0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm			0	1	0.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm			0	1	0.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm			0	1	0.00
V2S	sec_cm_ctr_redun	edn_sec_cm			0	1	0.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert			0	1	0.00
		edn_sec_cm			0	1	0.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert			0	1	0.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.860s	314.493us	1	1	100.00
V2S		TOTAL			1	3	33.33
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset			0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			9	21	42.86

Failure Buckets

• Job killed most likely because its dependent job failed. has 12 failures:

  • Test edn_smoke has 1 failures.

    • 0.edn_smoke.53479491657886187499519229996150723643922268789915346222549071718580145062338
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_smoke/latest/run.log

  • Test edn_regwen has 1 failures.

    • 0.edn_regwen.101862372485485669734302259875047682055520565835988665750572131367405569087381
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_regwen/latest/run.log

  • Test edn_genbits has 1 failures.

    • 0.edn_genbits.508176126272191362088059197966506074284777930642168261049453223552412341248
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_genbits/latest/run.log

  • Test edn_stress_all has 1 failures.

    • 0.edn_stress_all.81808792159834361398057663357106527647224606707039898114355941612040342610567
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all/latest/run.log

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.86177156099187150797050200905925095950919634153542076824474940997641011799497
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

  • ... and 7 more tests.

• Job timed out after * minutes has 1 failures:
  • Test default has 1 failures.

    • default
      Log /nightly/current_run/scratch/master/edn-sim-vcs/default/build.log

        Job timed out after 60 minutes