HMAC Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	18.173s		0	1	0.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.790s	73.604us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.620s	29.461us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.020s	1.628ms	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	4.240s	385.341us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	0.820s	15.295us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.620s	29.461us	1	1	100.00
		hmac_csr_aliasing	4.240s	385.341us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	long_msg	hmac_long_msg	16.080s	1.710ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	38.820s	3.562ms	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	7.350s	464.032us	1	1	100.00
		hmac_test_sha384_vectors	17.070s	200.786us	1	1	100.00
		hmac_test_sha512_vectors	18.360s	1.042ms	1	1	100.00
		hmac_test_hmac256_vectors	5.660s	1.145ms	1	1	100.00
		hmac_test_hmac384_vectors	8.800s	1.338ms	1	1	100.00
		hmac_test_hmac512_vectors	10.570s	386.075us	1	1	100.00
V2	burst_wr	hmac_burst_wr	13.200s	7.720ms	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	2.625m	2.891ms	1	1	100.00
V2	error	hmac_error	6.230s	142.960us	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	59.540s	20.977ms	1	1	100.00
V2	save_and_restore	hmac_smoke	18.173s		0	1	0.00
		hmac_long_msg	16.080s	1.710ms	1	1	100.00
		hmac_back_pressure	38.820s	3.562ms	1	1	100.00
		hmac_datapath_stress	2.625m	2.891ms	1	1	100.00
		hmac_burst_wr	13.200s	7.720ms	1	1	100.00
		hmac_stress_all	13.860s	1.528ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	18.173s		0	1	0.00
		hmac_long_msg	16.080s	1.710ms	1	1	100.00
		hmac_back_pressure	38.820s	3.562ms	1	1	100.00
		hmac_datapath_stress	2.625m	2.891ms	1	1	100.00
		hmac_wipe_secret	59.540s	20.977ms	1	1	100.00
		hmac_test_sha256_vectors	7.350s	464.032us	1	1	100.00
		hmac_test_sha384_vectors	17.070s	200.786us	1	1	100.00
		hmac_test_sha512_vectors	18.360s	1.042ms	1	1	100.00
		hmac_test_hmac256_vectors	5.660s	1.145ms	1	1	100.00
		hmac_test_hmac384_vectors	8.800s	1.338ms	1	1	100.00
		hmac_test_hmac512_vectors	10.570s	386.075us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	18.173s		0	1	0.00
		hmac_long_msg	16.080s	1.710ms	1	1	100.00
		hmac_back_pressure	38.820s	3.562ms	1	1	100.00
		hmac_datapath_stress	2.625m	2.891ms	1	1	100.00
		hmac_burst_wr	13.200s	7.720ms	1	1	100.00
		hmac_error	6.230s	142.960us	1	1	100.00
		hmac_wipe_secret	59.540s	20.977ms	1	1	100.00
		hmac_test_sha256_vectors	7.350s	464.032us	1	1	100.00
		hmac_test_sha384_vectors	17.070s	200.786us	1	1	100.00
		hmac_test_sha512_vectors	18.360s	1.042ms	1	1	100.00
		hmac_test_hmac256_vectors	5.660s	1.145ms	1	1	100.00
		hmac_test_hmac384_vectors	8.800s	1.338ms	1	1	100.00
		hmac_test_hmac512_vectors	10.570s	386.075us	1	1	100.00
		hmac_stress_all	13.860s	1.528ms	1	1	100.00
V2	stress_all	hmac_stress_all	13.860s	1.528ms	1	1	100.00
V2	alert_test	hmac_alert_test	0.570s	16.060us	1	1	100.00
V2	intr_test	hmac_intr_test	0.560s	13.812us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.420s	167.648us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.420s	167.648us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.790s	73.604us	1	1	100.00
		hmac_csr_rw	0.620s	29.461us	1	1	100.00
		hmac_csr_aliasing	4.240s	385.341us	1	1	100.00
		hmac_same_csr_outstanding	1.340s	193.685us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.790s	73.604us	1	1	100.00
		hmac_csr_rw	0.620s	29.461us	1	1	100.00
		hmac_csr_aliasing	4.240s	385.341us	1	1	100.00
		hmac_same_csr_outstanding	1.340s	193.685us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	0.750s	144.881us	1	1	100.00
		hmac_tl_intg_err	3.010s	918.162us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.010s	918.162us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	18.173s		0	1	0.00
V3	stress_reset	hmac_stress_reset	0.890s	59.801us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	33.730s	7.501ms	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.580s	324.078us	1	1	100.00
		TOTAL			27	28	96.43

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test hmac_smoke has 1 failures.

    • 0.hmac_smoke.112818233224412924447120918207850096744201695454963723200802368188858048976202
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_smoke/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:08 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255