I2C Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.360s	1.133ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.190s	982.694us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.670s	20.717us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.620s	40.644us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.380s	907.471us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.050s	542.310us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.140s	33.673us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.620s	40.644us	1	1	100.00
		i2c_csr_aliasing	1.050s	542.310us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.640s	15.253us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.815m	17.797ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.539m	18.358ms	1	1	100.00
V2	host_override	i2c_host_override	0.670s	28.909us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.511m	2.464ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	32.700s	4.143ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.090s	177.659us	1	1	100.00
		i2c_host_fifo_fmt_empty	2.960s	221.244us	1	1	100.00
		i2c_host_fifo_reset_rx	2.190s	241.137us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.843m	3.173ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.140s	709.383us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.820s	33.544us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.840s	1.624ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	50.610s	49.469ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.630s	485.713us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	22.590s	3.045ms	1	1	100.00
		i2c_target_intr_smoke	3.560s	3.706ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.040s	222.673us	1	1	100.00
		i2c_target_fifo_reset_tx	0.790s	123.651us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.169m	35.869ms	1	1	100.00
		i2c_target_stress_rd	22.590s	3.045ms	1	1	100.00
		i2c_target_intr_stress_wr	27.260s	10.141ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.260s	1.318ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	27.120s	2.641ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.990s	955.562us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.430s	10.108ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.240s	890.917us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.220s	748.711us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.539m	18.358ms	1	1	100.00
		i2c_host_perf_precise	2.030s	223.825us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.140s	709.383us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	8.890s	1.147ms	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.920s	2.488ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.650s	2.554ms	1	1	100.00
		i2c_target_nack_txstretch	1.100s	174.593us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.650s	301.355us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen			0	1	0.00
V2	alert_test	i2c_alert_test	0.600s	73.890us	1	1	100.00
V2	intr_test	i2c_intr_test	0.630s	20.487us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.840s	111.299us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.840s	111.299us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.670s	20.717us	1	1	100.00
		i2c_csr_rw	0.620s	40.644us	1	1	100.00
		i2c_csr_aliasing	1.050s	542.310us	1	1	100.00
		i2c_same_csr_outstanding	0.940s	101.251us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.670s	20.717us	1	1	100.00
		i2c_csr_rw	0.620s	40.644us	1	1	100.00
		i2c_csr_aliasing	1.050s	542.310us	1	1	100.00
		i2c_same_csr_outstanding	0.940s	101.251us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.150s	84.728us	1	1	100.00
		i2c_sec_cm	0.750s	216.136us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.150s	84.728us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.390s	178.805us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	18.067s		0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.200s	491.586us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.28565773435021945076577174609145539656043488453242583832854874325088208958075
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  15252561 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  15252561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.111009154202768206074481901719792551514232680449942446135857251674106470451395
      Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 17797482575 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 17797482575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.3636555720685891761150148816764045826052117525795252240688518539023858939980
      Line 136, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 178805375 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 178805375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.81482075399394413487780778627906139170479088066579997133324024375247218837346
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 491585840 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 491585840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.58365867844138145054352797556863177109873762207677042787097726571004784099992
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1624340857 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1624340857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.61754431637666368879841251538786463425329048439859395951379835923454866498347
      Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:22 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.7084889504878493475867788116273492411295409799744941893033936584687488202838
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10107845967 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10107845967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.101512856509121095614241941872911044544085627047939455164471979389320564939297
      Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  33543841 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• Job timed out after * minutes has 1 failures:

  • Test i2c_target_smbus_maxlen has 1 failures.

    • 0.i2c_target_smbus_maxlen.64443983092891725325294142926136828663903584261710837143501424451972907555173
      Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest/run.log

        Job timed out after 60 minutes