KEYMGR Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	17.957s		0	1	0.00
V1	random	keymgr_random	2.750s	176.044us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.750s	15.236us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.940s	54.563us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.360s	944.594us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.390s	627.340us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	32.527s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.940s	54.563us	1	1	100.00
		keymgr_csr_aliasing	3.390s	627.340us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	2.160s	37.289us	1	1	100.00
V2	sideload	keymgr_sideload	1.910s	47.354us	1	1	100.00
		keymgr_sideload_kmac	1.710s	36.102us	1	1	100.00
		keymgr_sideload_aes	1.320s	21.224us	1	1	100.00
		keymgr_sideload_otbn	24.473s		0	1	0.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.880s	573.312us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	1.700s	125.719us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.040s	315.111us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.470s	74.112us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	18.292s		0	1	0.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.000s	243.020us	1	1	100.00
V2	stress_all	keymgr_stress_all	6.670s	219.504us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.650s	50.826us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.800s	27.430us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.190s	126.099us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.190s	126.099us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.750s	15.236us	1	1	100.00
		keymgr_csr_rw	0.940s	54.563us	1	1	100.00
		keymgr_csr_aliasing	3.390s	627.340us	1	1	100.00
		keymgr_same_csr_outstanding	1.730s	60.908us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.750s	15.236us	1	1	100.00
		keymgr_csr_rw	0.940s	54.563us	1	1	100.00
		keymgr_csr_aliasing	3.390s	627.340us	1	1	100.00
		keymgr_same_csr_outstanding	1.730s	60.908us	1	1	100.00
V2		TOTAL			14	16	87.50
V2S	sec_cm_additional_check	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
		keymgr_tl_intg_err	5.480s	368.050us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.410s	394.129us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.410s	394.129us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.410s	394.129us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.410s	394.129us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.610s	258.073us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.480s	368.050us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.410s	394.129us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.160s	37.289us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.750s	176.044us	1	1	100.00
		keymgr_csr_rw	0.940s	54.563us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.750s	176.044us	1	1	100.00
		keymgr_csr_rw	0.940s	54.563us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.750s	176.044us	1	1	100.00
		keymgr_csr_rw	0.940s	54.563us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	1.700s	125.719us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	18.292s		0	1	0.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	18.292s		0	1	0.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.750s	176.044us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.220s	18.984us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	17.931s		0	1	0.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	1.700s	125.719us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	17.931s		0	1	0.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	17.931s		0	1	0.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	17.931s		0	1	0.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.820s	824.215us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	17.931s		0	1	0.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.210s	104.911us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	30	80.00

Failure Buckets

• Job returned non-zero exit code has 5 failures:

  • Test keymgr_smoke has 1 failures.

    • 0.keymgr_smoke.78870897661748684815453929667189337450663602640663566122170954182437805176961
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_smoke/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_sideload_otbn has 1 failures.

    • 0.keymgr_sideload_otbn.12626741370600939028392860331926438244880326364319101904153655203026363335876
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 0.keymgr_hwsw_invalid_input.102774408247660807500128580331170893199150196880467687883392509166133621797238
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_custom_cm has 1 failures.

    • 0.keymgr_custom_cm.111840782794546603208183845704552579559819301708183711131373098649863705496850
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_custom_cm/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.40572958652625354567581315305444277106647629014353373512407398947589368308171
      Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:09 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.7332351062273552341120464571729150239140993919393178209238550897188946425813
      Line 205, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 104910588 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 104910588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---