bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 23.060s | 760.503us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | kmac_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | kmac_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | kmac_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0 | 1 | 0.00 | ||
| kmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | kmac_mem_walk | 0 | 1 | 0.00 | ||
| V1 | mem_partial_access | kmac_mem_partial_access | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 1 | 8 | 12.50 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 21.970m | 114.734ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 1.669m | 7.228ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 19.899s | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_256 | 16.317m | 65.727ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 12.216m | 13.422ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 11.850s | 2.064ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.454m | 4.289ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 3.765m | 19.331ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 1.430s | 80.178us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 1.740s | 79.425us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 4.287m | 46.328ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 3.075m | 46.808ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 21.965s | 0 | 1 | 0.00 | |
| V2 | entropy_refresh | kmac_entropy_refresh | 1.997m | 40.261ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 47.440s | 2.716ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 3.910s | 4.424ms | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 1.090s | 73.675us | 1 | 1 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 8.760s | 1.981ms | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 20.450s | 456.291us | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 28.430s | 7.800ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 4.790s | 249.147us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 26.812m | 462.676ms | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0 | 1 | 0.00 | ||
| V2 | alert_test | kmac_alert_test | 0.720s | 28.680us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | kmac_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| kmac_csr_rw | 0 | 1 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| kmac_csr_rw | 0 | 1 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 21 | 26 | 80.77 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 0 | 1 | 0.00 | ||
| V2S | tl_intg_err | kmac_sec_cm | 47.720s | 7.699ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 4.790s | 249.147us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 23.060s | 760.503us | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 4.287m | 46.328ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 47.720s | 7.699ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 47.720s | 7.699ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 47.720s | 7.699ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 23.060s | 760.503us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 4.790s | 249.147us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 47.720s | 7.699ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 20.330s | 0 | 1 | 0.00 | |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 23.060s | 760.503us | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 5 | 20.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.075m | 3.068ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 23 | 40 | 57.50 |
Job killed most likely because its dependent job failed. has 13 failures:
Test kmac_shadow_reg_errors has 1 failures.
Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
Test kmac_mem_walk has 1 failures.
Test kmac_mem_partial_access has 1 failures.
Test kmac_tl_errors has 1 failures.
... and 8 more tests.
Job returned non-zero exit code has 3 failures:
Test kmac_test_vectors_sha3_224 has 1 failures.
0.kmac_test_vectors_sha3_224.68813380029399955563309890729160870738051544060918414418339618054963197184582
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 16:11 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_app_with_partial_data has 1 failures.
0.kmac_app_with_partial_data.21395808933892596089314494850174270871597095172852960766181749998830635691747
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 16:11 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_mubi has 1 failures.
0.kmac_mubi.37322886460982309119046109841949165562010411290596858500097543372929717871638
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 18 16:11 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.kmac_stress_all_with_rand_reset.13192286728102210656077232749780306862708762135436576903411021773430857892593
Line 232, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3068289304 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3068289304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---