bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 3.440s | 418.291us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 1 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 1 | 8 | 12.50 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 4.150s | 569.955us | 1 | 1 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 14.370s | 4.293ms | 1 | 1 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 6.370s | 240.368us | 1 | 1 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 4.110s | 166.538us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 4 | 6 | 66.67 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 3.121m | 917.536us | 0 | 1 | 0.00 |
| rom_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 3.121m | 917.536us | 0 | 1 | 0.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 3.121m | 917.536us | 0 | 1 | 0.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 3.121m | 917.536us | 0 | 1 | 0.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 3.121m | 917.536us | 0 | 1 | 0.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 3.440s | 418.291us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 3.440s | 418.291us | 1 | 1 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 3.440s | 418.291us | 1 | 1 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| rom_ctrl_kmac_err_chk | 6.370s | 240.368us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 50.590s | 13.425ms | 0 | 1 | 0.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 3.121m | 917.536us | 0 | 1 | 0.00 |
| V2S | TOTAL | 0 | 4 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 44.940s | 3.925ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 6 | 19 | 31.58 |
Job killed most likely because its dependent job failed. has 11 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
Test rom_ctrl_tl_errors has 1 failures.
Test rom_ctrl_tl_intg_err has 1 failures.
Test rom_ctrl_mem_walk has 1 failures.
Test rom_ctrl_mem_partial_access has 1 failures.
... and 6 more tests.
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
0.rom_ctrl_corrupt_sig_fatal_chk.78057586270205018946696663699606513125117289430441939439313683014810321323615
Line 97, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 13425348888 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 13425348888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
0.rom_ctrl_sec_cm.91311971641334241180612719924038419289722764867078853758282176588889578668864
Line 246, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 32523124ps failed at 32523124ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 32523124ps failed at 32523124ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'