ROM_CTRL/64KB Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.280s	1.106ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.010s	290.667us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.400s	1.070ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.540s	357.099us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.860s	289.424us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.400s	1.179ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.400s	1.070ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.860s	289.424us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.840s	292.375us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.290s	699.360us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.200s	1.777ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	28.860s	1.098ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.470s	1.272ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	5.420s	2.102ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.320s	535.430us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.320s	535.430us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.010s	290.667us	1	1	100.00
		rom_ctrl_csr_rw	6.400s	1.070ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.860s	289.424us	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.690s	2.088ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.010s	290.667us	1	1	100.00
		rom_ctrl_csr_rw	6.400s	1.070ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.860s	289.424us	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.690s	2.088ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	21.710s	1.418ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.609m	407.888us	0	1	0.00
		rom_ctrl_tl_intg_err	48.880s	1.348ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.609m	407.888us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.609m	407.888us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.609m	407.888us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.609m	407.888us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.280s	1.106ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.280s	1.106ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.280s	1.106ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	48.880s	1.348ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
		rom_ctrl_kmac_err_chk	11.470s	1.272ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.901m	4.010ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	21.710s	1.418ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.609m	407.888us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	20.404s		0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.84010353741054373417495044392507056676949818226447198793174908546121461992261
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:23 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.80344306703051953236760371314417533815814080218719984444185593931695411522009
      Line 234, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 12250751ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 12250751ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 12250751ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))