RV_TIMER Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.710s	128.823us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.560s	17.562us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.570s	42.962us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.740s	116.958us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.650s	55.854us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.760s	131.073us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.570s	42.962us	1	1	100.00
		rv_timer_csr_aliasing	0.650s	55.854us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.560s	179.464us	1	1	100.00
V2	disabled	rv_timer_disabled	0.930s	2.883ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.990s	12.584ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.990s	12.584ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.280s	4.569ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.610s	14.858us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.500s	12.350us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	0.840s	398.856us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	0.840s	398.856us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.560s	17.562us	1	1	100.00
		rv_timer_csr_rw	0.570s	42.962us	1	1	100.00
		rv_timer_csr_aliasing	0.650s	55.854us	1	1	100.00
		rv_timer_same_csr_outstanding	0.610s	72.580us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.560s	17.562us	1	1	100.00
		rv_timer_csr_rw	0.570s	42.962us	1	1	100.00
		rv_timer_csr_aliasing	0.650s	55.854us	1	1	100.00
		rv_timer_same_csr_outstanding	0.610s	72.580us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	0.790s	61.172us	1	1	100.00
		rv_timer_tl_intg_err	0.910s	274.791us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.910s	274.791us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	9.880s	886.344us	0	1	0.00
V3	max_value	rv_timer_max	0.570s	168.856us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	12.040s	1.381ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			17	19	89.47

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.71773052516240353263277369213922077124263151513487615118554626208749283028532
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 886344092 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb5139304) == 0x1
        UVM_INFO @ 886344092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.12763686190450992907842532459374915335883215069187166978752020240894431625618
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 168855911 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 168855911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---