SPI_DEVICE/1R1W Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	46.590s	6.573ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.800s	74.097us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.350s	367.782us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.380s	6.263ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.360s	1.048ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.280s	30.687us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.350s	367.782us	1	1	100.00
		spi_device_csr_aliasing	14.360s	1.048ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.640s	37.498us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.010s	56.983us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.750s	325.202us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.640s	1.724us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.660s	3.220us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.830s	290.355us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.830s	290.355us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.520s	10.790ms	1	1	100.00
		spi_device_tpm_sts_read	0.680s	99.741us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.497s		0	1	0.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.780s	5.742ms	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.910s	12.774ms	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.910s	12.774ms	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.220s	980.707us	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.220s	980.707us	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.220s	980.707us	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.220s	980.707us	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.220s	980.707us	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.820s	110.461us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	50.580s	8.499ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	50.580s	8.499ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	50.580s	8.499ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.300s	111.314us	1	1	100.00
		spi_device_read_buffer_direct	22.168s		0	1	0.00
V2	cmd_dummy_cycle	spi_device_mailbox	50.580s	8.499ms	1	1	100.00
		spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.081m	11.712ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.330s	913.664us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.330s	913.664us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	46.590s	6.573ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.330s	1.993ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.480m	50.324ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.640s	38.119us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.670s	16.739us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	24.333s		0	1	0.00
V2	tl_d_illegal_access	spi_device_tl_errors	24.333s		0	1	0.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.800s	74.097us	1	1	100.00
		spi_device_csr_rw	1.350s	367.782us	1	1	100.00
		spi_device_csr_aliasing	14.360s	1.048ms	1	1	100.00
		spi_device_same_csr_outstanding	2.870s	69.854us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.800s	74.097us	1	1	100.00
		spi_device_csr_rw	1.350s	367.782us	1	1	100.00
		spi_device_csr_aliasing	14.360s	1.048ms	1	1	100.00
		spi_device_same_csr_outstanding	2.870s	69.854us	1	1	100.00
V2		TOTAL			17	22	77.27
V2S	tl_intg_err	spi_device_sec_cm	0.960s	90.346us	1	1	100.00
		spi_device_tl_intg_err	13.910s		0	1	0.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.910s		0	1	0.00
V2S		TOTAL			1	2	50.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.540s	1.075ms	1	1	100.00
		TOTAL			27	33	81.82

Failure Buckets

• Job returned non-zero exit code has 4 failures:

  • Test spi_device_tpm_all has 1 failures.

    • 0.spi_device_tpm_all.20948863437545757321722418455417063723612974026176216077713125201646688583294
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:16 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test spi_device_read_buffer_direct has 1 failures.

    • 0.spi_device_read_buffer_direct.80827418482877811115094170482941579832625730546660393853530126309585268232804
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:16 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test spi_device_tl_errors has 1 failures.

    • 0.spi_device_tl_errors.39324492307519621268899469665508937658832105514670916880200936625110892444509
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:15 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test spi_device_tl_intg_err has 1 failures.

    • 0.spi_device_tl_intg_err.80874061832501436938817090380872103379080304046517983258116179152676818430798
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:15 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.80148653828988736963286859484152494658762144032126794787455601621949380028283
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1243164 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[108])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1243164 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1243164 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1004])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.73078873713875713241615201807888648003009578081655718471532863580862466467293
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    930039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6213e8 [11000100001001111101000] vs 0x0 [0])
        UVM_ERROR @    968039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa16699 [101000010110011010011001] vs 0x0 [0])
        UVM_ERROR @   1027039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcf7fd4 [110011110111111111010100] vs 0x0 [0])
        UVM_ERROR @   1081039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb8ccd1 [101110001100110011010001] vs 0x0 [0])
        UVM_ERROR @   1171039 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7a4a66 [11110100100101001100110] vs 0x0 [0])