bddb67a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 10.670s | 518.799us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | sram_ctrl_mem_walk | 1.957m | 47.040ms | 1 | 1 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 49.690s | 2.769ms | 1 | 1 | 100.00 |
| V1 | TOTAL | 3 | 8 | 37.50 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 4.950m | 26.199ms | 1 | 1 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 3.733m | 10.274ms | 1 | 1 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 25.488m | 473.576ms | 1 | 1 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 2.947m | 7.252ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 43.210s | 207.533ms | 1 | 1 | 100.00 |
| V2 | executable | sram_ctrl_executable | 10.109m | 278.343ms | 1 | 1 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 24.180s | 1.489ms | 1 | 1 | 100.00 |
| sram_ctrl_partial_access_b2b | 4.008m | 22.607ms | 1 | 1 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 22.650s | 5.596ms | 1 | 1 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 38.430s | 3.739ms | 1 | 1 | 100.00 | ||
| sram_ctrl_throughput_w_readback | 5.520s | 1.796ms | 1 | 1 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 3.147m | 10.529ms | 1 | 1 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 2.270s | 1.305ms | 1 | 1 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 18.360m | 49.996ms | 1 | 1 | 100.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.690s | 175.840us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0 | 1 | 0.00 | ||
| sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||||
| sram_ctrl_csr_aliasing | 0 | 1 | 0.00 | ||||
| sram_ctrl_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 15 | 17 | 88.24 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.610s | 3.484us | 0 | 1 | 0.00 |
| sram_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.610s | 3.484us | 0 | 1 | 0.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 3.147m | 10.529ms | 1 | 1 | 100.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 3.147m | 10.529ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0 | 1 | 0.00 | ||
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 10.109m | 278.343ms | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 10.109m | 278.343ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 10.109m | 278.343ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 43.210s | 207.533ms | 1 | 1 | 100.00 |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 3.450s | 700.769us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 3.870s | 2.659ms | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 10.670s | 518.799us | 1 | 1 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 10.670s | 518.799us | 1 | 1 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 10.109m | 278.343ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.610s | 3.484us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 43.210s | 207.533ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.610s | 3.484us | 0 | 1 | 0.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.610s | 3.484us | 0 | 1 | 0.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 10.670s | 518.799us | 1 | 1 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.610s | 3.484us | 0 | 1 | 0.00 |
| V2S | TOTAL | 2 | 5 | 40.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 16.280s | 887.288us | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 21 | 31 | 67.74 |
Job killed most likely because its dependent job failed. has 9 failures:
Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
Test sram_ctrl_tl_errors has 1 failures.
Test sram_ctrl_tl_intg_err has 1 failures.
Test sram_ctrl_csr_hw_reset has 1 failures.
Test sram_ctrl_csr_rw has 1 failures.
... and 4 more tests.
Job timed out after * minutes has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/cover_reg_top/build.log
Job timed out after 60 minutes
Offending '(depth_o <= *'(Depth))' has 1 failures:
0.sram_ctrl_sec_cm.85260316563251851705996418020130527425647995126920651715574799127942672320762
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 3484107 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 3484107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---