SRAM_CTRL/RET Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	33.590s	588.002us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	23.808s		0	1	0.00
V1	csr_rw	sram_ctrl_csr_rw	0.640s	13.033us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.100s	124.713us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.660s	54.346us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.120s	156.877us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.640s	13.033us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	54.346us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.940s	990.274us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.130s	65.734us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	7.501m	13.085ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.381m	2.295ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.380s	333.577us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.391m	1.425ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.080s	711.279us	1	1	100.00
V2	executable	sram_ctrl_executable	1.321m	3.357ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.940s	2.294ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.837m	128.991ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.400s	83.763us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.640s	70.446us	1	1	100.00
		sram_ctrl_throughput_w_readback	33.560s	290.585us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.096m	24.757ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.670s	81.247us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	30.664m	98.327ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.590s	15.613us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.990s	284.767us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.990s	284.767us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	23.808s		0	1	0.00
		sram_ctrl_csr_rw	0.640s	13.033us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	54.346us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.640s	43.945us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	23.808s		0	1	0.00
		sram_ctrl_csr_rw	0.640s	13.033us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	54.346us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.640s	43.945us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.580s	6.934ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.590s	8.235us	0	1	0.00
		sram_ctrl_tl_intg_err	1.650s	637.246us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.590s	8.235us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.650s	637.246us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.096m	24.757ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.096m	24.757ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.640s	13.033us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.321m	3.357ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.321m	3.357ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.321m	3.357ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.080s	711.279us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.900s	65.459us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.580s	6.934ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.780s	34.760us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	33.590s	588.002us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	33.590s	588.002us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.321m	3.357ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.590s	8.235us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.080s	711.279us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.590s	8.235us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.590s	8.235us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	33.590s	588.002us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.590s	8.235us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.409m	33.871ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.53502551832358518003042853389800088466637548878757340647855124020052970702253
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8234905 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8234905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test sram_ctrl_csr_hw_reset has 1 failures.

    • 0.sram_ctrl_csr_hw_reset.112346857122471068588520725923529097924217768922261749033300799392736265460542
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest/run.log

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