UART Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: bddb67a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.280s	292.384us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	54.847us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.590s	14.711us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.170s	68.559us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.590s	20.981us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.710s	26.433us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.590s	14.711us	1	1	100.00
		uart_csr_aliasing	0.590s	20.981us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	22.001s		0	1	0.00
V2	parity	uart_smoke	1.280s	292.384us	1	1	100.00
		uart_tx_rx	22.001s		0	1	0.00
V2	parity_error	uart_intr	11.400s	34.674ms	1	1	100.00
		uart_rx_parity_err	1.044m	50.961ms	1	1	100.00
V2	watermark	uart_tx_rx	22.001s		0	1	0.00
		uart_intr	11.400s	34.674ms	1	1	100.00
V2	fifo_full	uart_fifo_full	12.810s	26.893ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	33.700s	32.348ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	17.710s	21.132ms	1	1	100.00
V2	rx_frame_err	uart_intr	11.400s	34.674ms	1	1	100.00
V2	rx_break_err	uart_intr	11.400s	34.674ms	1	1	100.00
V2	rx_timeout	uart_intr	11.400s	34.674ms	1	1	100.00
V2	perf	uart_perf	5.511m	20.719ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.960s	5.533ms	1	1	100.00
V2	line_loopback	uart_loopback	2.960s	5.533ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.280s	1.613ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.230s	1.672ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.970s	1.652ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	41.160s	7.731ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.269m	246.530ms	1	1	100.00
V2	stress_all	uart_stress_all	18.238s		0	1	0.00
V2	alert_test	uart_alert_test	22.479s		0	1	0.00
V2	intr_test	uart_intr_test	0.690s	36.271us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.240s	64.489us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.240s	64.489us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	54.847us	1	1	100.00
		uart_csr_rw	0.590s	14.711us	1	1	100.00
		uart_csr_aliasing	0.590s	20.981us	1	1	100.00
		uart_same_csr_outstanding	0.670s	187.756us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	54.847us	1	1	100.00
		uart_csr_rw	0.590s	14.711us	1	1	100.00
		uart_csr_aliasing	0.590s	20.981us	1	1	100.00
		uart_same_csr_outstanding	0.670s	187.756us	1	1	100.00
V2		TOTAL			14	18	77.78
V2S	tl_intg_err	uart_sec_cm	0.780s	263.353us	1	1	100.00
		uart_tl_intg_err	0.860s	93.694us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.860s	93.694us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.100s	6.057ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			23	27	85.19

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test uart_tx_rx has 1 failures.

    • 0.uart_tx_rx.753367166257009643622089543827221738231287428521370672339016040809040239721
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_tx_rx/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:14 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.42329362100017288846715110349867026304753624323691194172271066475698256789636
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:14 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test uart_alert_test has 1 failures.

    • 0.uart_alert_test.8518518860978883606308373027982970625237606470366538474565991606537064203433
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_alert_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 18 16:14 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.109274996566562517130353319186612753519853196373963613753752958498058589023105
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 356871098 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 356881624 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 356892150 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 372702202 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 372702202 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1