CHIP Simulation Results

Thursday September 18 2025 16:06:50 UTC

GitHub Revision: `bddb67a`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	14.597s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	14.597s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	10.362s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	10.260s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.563s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	12.719s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	12.719s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	12.719s		0	1	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	15.141s		0	1	0.00
		chip_sw_example_manufacturer	13.521s		0	1	0.00
		chip_sw_example_concurrency	11.269s		0	1	0.00
		chip_sw_uart_smoketest_signed	10.581s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	7.880s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	7.820s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	7.820s		0	1	0.00
V1	xbar_smoke	xbar_smoke	7.630s	11.987us	1	1	100.00
V1		TOTAL			1	12	8.33
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	14.373s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.940s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	13.351s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	14.888s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	15.056s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.777s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	14.778s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.710s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.710s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.362s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	14.424s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	10.555s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	10.555s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	43.340s		0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.341m	4.009ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	17.985s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.641s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.326s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	31.709s		0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	10.481s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.582s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.582s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	18.964s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.425s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.425s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	19.349s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	18.859s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.971s		0	1	0.00
		chip_sw_aes_idle	15.057s		0	1	0.00
		chip_sw_hmac_enc_idle	18.416s		0	1	0.00
		chip_sw_kmac_idle	19.034s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	17.611s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	17.657s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	10.799s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	18.811s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	18.928s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.389s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.601s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.166s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.543s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.441s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.928s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.389s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.601s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.166s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.543s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.441s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.324s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.338s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	18.800s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	10.490s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.165s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.384s		0	1	0.00
		chip_sw_clkmgr_jitter	18.333s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	45.672s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	53.233s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	32.710s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.448m		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	33.120s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	33.335s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	2.003m		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	52.995s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.420s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	18.342s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	18.948s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	10.463s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	17.918s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	18.425s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	18.799s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	17.918s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.411s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	10.480s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.641s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.295s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.533s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	10.463s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	17.985s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	17.955s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	17.744s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.795s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	17.962s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	10.463s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.286s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.577s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	10.463s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	20.071s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.795s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.412s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.917s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.028s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.304s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.570s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.908s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.577s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	12.412s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	13.268s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.298s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.300s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.246s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.249s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	18.523s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	18.543s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	18.442s		0	1	0.00
		chip_prim_tl_access	15.002m	26.712ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.928s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.389s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.601s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.166s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.543s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.441s		0	1	0.00
		chip_rv_dm_lc_disabled	31.709s		0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	15.725s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.338s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	18.703s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	15.057s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	18.422s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	18.800s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	18.416s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	18.705s		0	1	0.00
		chip_sw_kmac_mode_kmac	19.681s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.165s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	18.523s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	18.596s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	10.414s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	19.034s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	19.300s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	19.300s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	19.676s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	18.649s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	19.570s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	18.523s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	10.490s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.994s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	16.324s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	16.971s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	16.971s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	16.971s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	16.318s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	18.543s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	18.543s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	19.039s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.384s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.442s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	10.463s		0	1	0.00
		chip_sw_data_integrity_escalation	10.555s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	16.318s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	18.523s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	19.039s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	53.294s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	16.318s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	18.523s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	19.039s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	53.294s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.348s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	12.412s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.298s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.300s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.246s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.249s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.672s		0	1	0.00
		chip_prim_tl_access	15.002m	26.712ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	15.002m	26.712ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.781s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	17.874s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.420s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.324s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.338s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	18.800s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	10.490s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.165s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.384s		0	1	0.00
		chip_sw_clkmgr_jitter	18.333s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.485s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.485s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	18.691s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	19.025s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	19.341s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	15.498s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	14.787s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	26.478s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	53.294s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	17.955s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	17.955s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.242m	4.417ms	1	1	100.00
		chip_sw_aon_timer_smoketest	1.179m		0	1	0.00
		chip_sw_clkmgr_smoketest	3.003m	5.085ms	1	1	100.00
		chip_sw_csrng_smoketest	3.544m	4.706ms	1	1	100.00
		chip_sw_gpio_smoketest	3.870m	5.731ms	1	1	100.00
		chip_sw_hmac_smoketest	3.821m	4.461ms	1	1	100.00
		chip_sw_kmac_smoketest	3.373m	4.913ms	1	1	100.00
		chip_sw_otbn_smoketest	3.967m	4.591ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.466m	5.184ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.970m	5.645ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.247m	6.011ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.095m	4.393ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.194m	5.265ms	1	1	100.00
		chip_sw_uart_smoketest	3.203m	5.337ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.882s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.581s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	14.373s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	1.847m		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	11.362s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	10.719s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	10.870s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	10.915s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.389s		0	1	0.00
		chip_rv_dm_lc_disabled	31.709s		0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	10.961s		0	1	0.00
		chip_sw_lc_walkthrough_prod	10.961s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	10.632s		0	1	0.00
		chip_sw_lc_walkthrough_rma	10.488s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.389s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	10.581s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.428s		0	1	0.00
		rom_volatile_raw_unlock	10.543s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.592s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	11.357s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	12.394s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.411m	5.052ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.411m	5.052ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	7.820s		0	1	0.00
		chip_same_csr_outstanding	7.800s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	7.820s		0	1	0.00
		chip_same_csr_outstanding	7.800s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.581m	297.627us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.500s	12.511us	1	1	100.00
		xbar_smoke_large_delays	3.538m	2.014ms	1	1	100.00
		xbar_smoke_slow_rsp	4.300m	1.772ms	1	1	100.00
		xbar_random_zero_delays	25.000s	28.006us	1	1	100.00
		xbar_random_large_delays	11.300m	6.522ms	1	1	100.00
		xbar_random_slow_rsp			0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	14.130s	14.269us	1	1	100.00
		xbar_error_and_unmapped_addr	22.390s	56.661us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	10.180s	29.365us	1	1	100.00
		xbar_error_and_unmapped_addr	22.390s	56.661us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.333m	392.664us	1	1	100.00
		xbar_access_same_device_slow_rsp	20.072m	8.238ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	58.040s	181.041us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.884m	1.317ms	1	1	100.00
		xbar_stress_all_with_error	14.955m	3.303ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	26.822m	3.550ms	1	1	100.00
		xbar_stress_all_with_reset_error	8.566m	360.176us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	3.197m		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	3.097m		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	3.731m		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	1.255m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2.737m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2.729m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2.956m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2.469m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	33.781s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.612m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.645m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.789m		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.645m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	2.685m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	2.263m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	2.237m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	2.196m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	2.227m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	2.120m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	2.339m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	2.371m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	2.282m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	2.075m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	2.305m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	2.206m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	2.057m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	2.006m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.942m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	1.737m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.199m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	1.004m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.719s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	39.756s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.798s		0	1	0.00
		rom_e2e_asm_init_dev	16.567s		0	1	0.00
		rom_e2e_asm_init_prod	32.882s		0	1	0.00
		rom_e2e_asm_init_prod_end	10.890s		0	1	0.00
		rom_e2e_asm_init_rma	10.829s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.883s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.327s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.430s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.012s		0	1	0.00
V2		TOTAL			30	205	14.63
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	14.564s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.675m	4.555ms	1	1	100.00
V2S		TOTAL			1	2	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.198s		0	1	0.00
		rom_e2e_jtag_debug_dev	23.966s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.987s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.176m		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	10.463s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.258s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.464s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	18.276s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	3.603m		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.198s		0	1	0.00
		rom_e2e_jtag_debug_dev	23.966s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.987s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	14.425s		0	1	0.00
		rom_e2e_jtag_inject_dev	13.152s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.420s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.995s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	10.357s		0	1	0.00
		chip_sw_entropy_src_kat_test	18.530s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	18.587s		0	1	0.00
		chip_plic_all_irqs_0	19.186s		0	1	0.00
		chip_plic_all_irqs_10	18.861s		0	1	0.00
		chip_sw_dma_inline_hashing	3.762m	5.469ms	1	1	100.00
		chip_sw_dma_abort	5.675m		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.736s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.508s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.706s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.604s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.800s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.497s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.701s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.650s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.598s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.748s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.131m	5.217ms	1	1	100.00
		chip_sw_mbx_smoketest	54.944s		0	1	0.00
		TOTAL			34	250	13.60

Failure Buckets

Job returned non-zero exit code has 207 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.104871384467063118416291013707511037554462968758495679416963723710571319961982
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp8095726749502042948/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp8095726749502042948/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp8095726749502042948/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1758:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted
  INFO: Elapsed time: 4.965s, Critical Path: 0.28s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.108086717067961007789293991507657186762866811472237419481276233916589758822223
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp15226750515412787262/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp15226750515412787262/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp15226750515412787262/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+hooks+manufacturer_test_hooks/BUILD.bazel:143:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted
  INFO: Elapsed time: 3.324s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.69901165005625867292240983960828639120557752619309160042060165195680978251229
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp14887118149399016535/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp14887118149399016535/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp14887118149399016535/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1703:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.851s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_all_escalation_resets has 1 failures.

0.chip_sw_all_escalation_resets.27566329004507301858292434498907259802389776039974547233616772194764056377379
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp820529593286355131/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp820529593286355131/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp820529593286355131/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD:303:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.092s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.63216739370105652225936477256242393666490326580334224859739329062035419943397
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp16905510668067644910/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp16905510668067644910/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp16905510668067644910/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD:303:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted
  INFO: Elapsed time: 0.078s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 202 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.72882618429444212618923544806728672710661653209854401658340256374484324543537
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.5500125741338467072857743080576954863753475394034334868458688985528325205034
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.76768161519453136416258827900156273787691417096522286418673724036977107828030
    Line 143, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 2 failures:
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.74378626102709501654242629278198950884679683254096192183488365810199118502426
    Line 476, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.62303132072422956302708245770716927469308184345351178317812258256530565810548
    Line 485, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41769) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.102844582669159100501290813784823522903671299549358639382412269563218216587519
Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5051.952940 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41769) { a_addr: 'h40634  a_data: 'h67fbd9ce  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h18923  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5051.952940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.20520013333354942372732084478722027529935009608857373508628986392263967766080
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4009.210692 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hd7a79433  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h1  a_user: 'h248eb  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4009.210692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.4298245683374534225157587540681128015757954668500612711358565551684245074855
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
Job timed out after * minutes has 1 failures:
- Test xbar_random_slow_rsp has 1 failures.
  - 0.xbar_random_slow_rsp.71839696183075299075019258478633837428407645453779419793752730756159638107858
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```