AES/MASKED Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 20.000s 0 1 0.00
V1 smoke aes_smoke 21.000s 0 1 0.00
V1 csr_hw_reset aes_csr_hw_reset 38.000s 0 1 0.00
V1 csr_rw aes_csr_rw 2.000s 70.173us 1 1 100.00
V1 csr_bit_bash aes_csr_bit_bash 21.000s 0 1 0.00
V1 csr_aliasing aes_csr_aliasing 21.000s 0 1 0.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 37.000s 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 2.000s 70.173us 1 1 100.00
aes_csr_aliasing 21.000s 0 1 0.00
V1 TOTAL 1 7 14.29
V2 algorithm aes_smoke 21.000s 0 1 0.00
aes_config_error 43.000s 0 1 0.00
aes_stress 25.000s 0 1 0.00
V2 key_length aes_smoke 21.000s 0 1 0.00
aes_config_error 43.000s 0 1 0.00
aes_stress 25.000s 0 1 0.00
V2 back2back aes_stress 25.000s 0 1 0.00
aes_b2b 29.000s 0 1 0.00
V2 backpressure aes_stress 25.000s 0 1 0.00
V2 multi_message aes_smoke 21.000s 0 1 0.00
aes_config_error 43.000s 0 1 0.00
aes_stress 25.000s 0 1 0.00
aes_alert_reset 43.000s 0 1 0.00
V2 failure_test aes_man_cfg_err 29.000s 0 1 0.00
aes_config_error 43.000s 0 1 0.00
aes_alert_reset 43.000s 0 1 0.00
V2 trigger_clear_test aes_clear 30.000s 0 1 0.00
V2 nist_test_vectors aes_nist_vectors 29.000s 0 1 0.00
V2 reset_recovery aes_alert_reset 43.000s 0 1 0.00
V2 stress aes_stress 25.000s 0 1 0.00
V2 sideload aes_stress 25.000s 0 1 0.00
aes_sideload 29.000s 0 1 0.00
V2 deinitialization aes_deinit 42.000s 0 1 0.00
V2 stress_all aes_stress_all 30.000s 0 1 0.00
V2 alert_test aes_alert_test 21.000s 0 1 0.00
V2 tl_d_oob_addr_access aes_tl_errors 21.000s 0 1 0.00
V2 tl_d_illegal_access aes_tl_errors 21.000s 0 1 0.00
V2 tl_d_outstanding_access aes_csr_hw_reset 38.000s 0 1 0.00
aes_csr_rw 2.000s 70.173us 1 1 100.00
aes_csr_aliasing 21.000s 0 1 0.00
aes_same_csr_outstanding 18.000s 0 1 0.00
V2 tl_d_partial_access aes_csr_hw_reset 38.000s 0 1 0.00
aes_csr_rw 2.000s 70.173us 1 1 100.00
aes_csr_aliasing 21.000s 0 1 0.00
aes_same_csr_outstanding 18.000s 0 1 0.00
V2 TOTAL 0 13 0.00
V2S reseeding aes_reseed 17.000s 0 1 0.00
V2S fault_inject aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
V2S shadow_reg_update_error aes_shadow_reg_errors 34.000s 0 1 0.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 34.000s 0 1 0.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 34.000s 0 1 0.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 34.000s 0 1 0.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 33.000s 0 1 0.00
V2S tl_intg_err aes_sec_cm 30.000s 0 1 0.00
aes_tl_intg_err 2.000s 189.064us 1 1 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 2.000s 189.064us 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 43.000s 0 1 0.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 34.000s 0 1 0.00
V2S sec_cm_main_config_sparse aes_smoke 21.000s 0 1 0.00
aes_stress 25.000s 0 1 0.00
aes_alert_reset 43.000s 0 1 0.00
aes_core_fi 30.000s 0 1 0.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 34.000s 0 1 0.00
V2S sec_cm_aux_config_regwen aes_readability 38.000s 0 1 0.00
aes_stress 25.000s 0 1 0.00
V2S sec_cm_key_sideload aes_stress 25.000s 0 1 0.00
aes_sideload 29.000s 0 1 0.00
V2S sec_cm_key_sw_unreadable aes_readability 38.000s 0 1 0.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 38.000s 0 1 0.00
V2S sec_cm_key_sec_wipe aes_readability 38.000s 0 1 0.00
V2S sec_cm_iv_config_sec_wipe aes_readability 38.000s 0 1 0.00
V2S sec_cm_data_reg_sec_wipe aes_readability 38.000s 0 1 0.00
V2S sec_cm_data_reg_key_sca aes_stress 25.000s 0 1 0.00
V2S sec_cm_key_masking aes_stress 25.000s 0 1 0.00
V2S sec_cm_main_fsm_sparse aes_fi 29.000s 0 1 0.00
V2S sec_cm_main_fsm_redun aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
aes_ctr_fi 33.000s 0 1 0.00
V2S sec_cm_cipher_fsm_sparse aes_fi 29.000s 0 1 0.00
V2S sec_cm_cipher_fsm_redun aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 36.000s 0 1 0.00
V2S sec_cm_ctr_fsm_sparse aes_fi 29.000s 0 1 0.00
V2S sec_cm_ctr_fsm_redun aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_ctr_fi 33.000s 0 1 0.00
V2S sec_cm_ctrl_sparse aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
aes_ctr_fi 33.000s 0 1 0.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 43.000s 0 1 0.00
V2S sec_cm_main_fsm_local_esc aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
aes_ctr_fi 33.000s 0 1 0.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
aes_ctr_fi 33.000s 0 1 0.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_ctr_fi 33.000s 0 1 0.00
V2S sec_cm_data_reg_local_esc aes_fi 29.000s 0 1 0.00
aes_control_fi 2.000s 52.393us 1 1 100.00
aes_cipher_fi 36.000s 0 1 0.00
V2S TOTAL 2 11 18.18
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 37.000s 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 3 32 9.38

Failure Buckets