359e412| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | aon_timer_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | aon_timer_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 0 | 1 | 0.00 | ||
| aon_timer_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | mem_walk | aon_timer_mem_walk | 0 | 1 | 0.00 | ||
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 0 | 8 | 0.00 | |||
| V2 | prescaler | aon_timer_prescaler | 0 | 1 | 0.00 | ||
| V2 | jump | aon_timer_jump | 0 | 1 | 0.00 | ||
| V2 | stress_all | aon_timer_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | aon_timer_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | aon_timer_intr_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 0 | 1 | 0.00 | ||
| aon_timer_csr_rw | 0 | 1 | 0.00 | ||||
| aon_timer_csr_aliasing | 0 | 1 | 0.00 | ||||
| aon_timer_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 0 | 1 | 0.00 | ||
| aon_timer_csr_rw | 0 | 1 | 0.00 | ||||
| aon_timer_csr_aliasing | 0 | 1 | 0.00 | ||||
| aon_timer_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 0 | 7 | 0.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 0 | 1 | 0.00 | ||
| aon_timer_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 0 | 2 | 0.00 | |||
| V3 | max_threshold | aon_timer_smoke_max_thold | 0 | 1 | 0.00 | ||
| V3 | min_threshold | aon_timer_smoke_min_thold | 0 | 1 | 0.00 | ||
| V3 | wkup_count_hi_cdc | aon_timer_wkup_count_cdc_hi | 0 | 1 | 0.00 | ||
| V3 | custom_intr | aon_timer_custom_intr | 0 | 1 | 0.00 | ||
| V3 | alternating_on_off | aon_timer_alternating_enable_on_off | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 6 | 0.00 | |||
| TOTAL | 0 | 23 | 0.00 |
Job killed most likely because its dependent job failed. has 23 failures:
Test aon_timer_smoke has 1 failures.
Test aon_timer_prescaler has 1 failures.
Test aon_timer_jump has 1 failures.
Test aon_timer_custom_intr has 1 failures.
Test aon_timer_smoke_max_thold has 1 failures.
... and 18 more tests.
Job timed out after * minutes has 1 failures:
default
Log /nightly/current_run/scratch/master/aon_timer-sim-vcs/default/build.log
Job timed out after 60 minutes
Job returned non-zero exit code has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/aon_timer-sim-vcs/cover_reg_top/build.log
recompiling module tb
All of 82 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 17.995 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1