EDN Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.830s 17.927us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.720s 12.976us 1 1 100.00
V1 csr_rw edn_csr_rw 0.710s 26.125us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.200s 94.327us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.120s 156.502us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.890s 228.312us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.710s 26.125us 1 1 100.00
edn_csr_aliasing 1.120s 156.502us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.100s 85.743us 1 1 100.00
V2 csrng_commands edn_genbits 1.100s 85.743us 1 1 100.00
V2 genbits edn_genbits 1.100s 85.743us 1 1 100.00
V2 interrupts edn_intr 0.910s 21.603us 1 1 100.00
V2 alerts edn_alert 0.890s 50.151us 1 1 100.00
V2 errs edn_err 0.820s 19.976us 1 1 100.00
V2 disable edn_disable 0.710s 22.890us 1 1 100.00
edn_disable_auto_req_mode 0.990s 72.865us 1 1 100.00
V2 stress_all edn_stress_all 2.150s 351.508us 1 1 100.00
V2 intr_test edn_intr_test 0.700s 45.639us 1 1 100.00
V2 alert_test edn_alert_test 0.730s 22.003us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 0.970s 63.255us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 0.970s 63.255us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.720s 12.976us 1 1 100.00
edn_csr_rw 0.710s 26.125us 1 1 100.00
edn_csr_aliasing 1.120s 156.502us 1 1 100.00
edn_same_csr_outstanding 0.830s 28.438us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.720s 12.976us 1 1 100.00
edn_csr_rw 0.710s 26.125us 1 1 100.00
edn_csr_aliasing 1.120s 156.502us 1 1 100.00
edn_same_csr_outstanding 0.830s 28.438us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 5.600s 887.392us 1 1 100.00
edn_tl_intg_err 1.780s 97.344us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.810s 51.207us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.890s 50.151us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.600s 887.392us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.600s 887.392us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.600s 887.392us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.600s 887.392us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.890s 50.151us 1 1 100.00
edn_sec_cm 5.600s 887.392us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.890s 50.151us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.780s 97.344us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets