359e412| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 3.220s | 372.603us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | hmac_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | hmac_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | hmac_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0 | 1 | 0.00 | ||
| hmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | TOTAL | 1 | 6 | 16.67 | |||
| V2 | long_msg | hmac_long_msg | 30.270s | 799.605us | 1 | 1 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 54.670s | 20.856ms | 1 | 1 | 100.00 |
| V2 | test_vectors | hmac_test_sha256_vectors | 12.042s | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 5.320m | 21.088ms | 1 | 1 | 100.00 | ||
| hmac_test_sha512_vectors | 4.822m | 9.117ms | 1 | 1 | 100.00 | ||
| hmac_test_hmac256_vectors | 8.090s | 265.688us | 1 | 1 | 100.00 | ||
| hmac_test_hmac384_vectors | 6.990s | 1.073ms | 1 | 1 | 100.00 | ||
| hmac_test_hmac512_vectors | 7.330s | 1.724ms | 1 | 1 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.170s | 76.986us | 1 | 1 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 4.782m | 13.481ms | 1 | 1 | 100.00 |
| V2 | error | hmac_error | 37.970s | 10.368ms | 1 | 1 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 5.000s | 623.954us | 1 | 1 | 100.00 |
| V2 | save_and_restore | hmac_smoke | 3.220s | 372.603us | 1 | 1 | 100.00 |
| hmac_long_msg | 30.270s | 799.605us | 1 | 1 | 100.00 | ||
| hmac_back_pressure | 54.670s | 20.856ms | 1 | 1 | 100.00 | ||
| hmac_datapath_stress | 4.782m | 13.481ms | 1 | 1 | 100.00 | ||
| hmac_burst_wr | 1.170s | 76.986us | 1 | 1 | 100.00 | ||
| hmac_stress_all | 55.950s | 1.677ms | 1 | 1 | 100.00 | ||
| V2 | fifo_empty_status_interrupt | hmac_smoke | 3.220s | 372.603us | 1 | 1 | 100.00 |
| hmac_long_msg | 30.270s | 799.605us | 1 | 1 | 100.00 | ||
| hmac_back_pressure | 54.670s | 20.856ms | 1 | 1 | 100.00 | ||
| hmac_datapath_stress | 4.782m | 13.481ms | 1 | 1 | 100.00 | ||
| hmac_wipe_secret | 5.000s | 623.954us | 1 | 1 | 100.00 | ||
| hmac_test_sha256_vectors | 12.042s | 0 | 1 | 0.00 | |||
| hmac_test_sha384_vectors | 5.320m | 21.088ms | 1 | 1 | 100.00 | ||
| hmac_test_sha512_vectors | 4.822m | 9.117ms | 1 | 1 | 100.00 | ||
| hmac_test_hmac256_vectors | 8.090s | 265.688us | 1 | 1 | 100.00 | ||
| hmac_test_hmac384_vectors | 6.990s | 1.073ms | 1 | 1 | 100.00 | ||
| hmac_test_hmac512_vectors | 7.330s | 1.724ms | 1 | 1 | 100.00 | ||
| V2 | wide_digest_configurable_key_length | hmac_smoke | 3.220s | 372.603us | 1 | 1 | 100.00 |
| hmac_long_msg | 30.270s | 799.605us | 1 | 1 | 100.00 | ||
| hmac_back_pressure | 54.670s | 20.856ms | 1 | 1 | 100.00 | ||
| hmac_datapath_stress | 4.782m | 13.481ms | 1 | 1 | 100.00 | ||
| hmac_burst_wr | 1.170s | 76.986us | 1 | 1 | 100.00 | ||
| hmac_error | 37.970s | 10.368ms | 1 | 1 | 100.00 | ||
| hmac_wipe_secret | 5.000s | 623.954us | 1 | 1 | 100.00 | ||
| hmac_test_sha256_vectors | 12.042s | 0 | 1 | 0.00 | |||
| hmac_test_sha384_vectors | 5.320m | 21.088ms | 1 | 1 | 100.00 | ||
| hmac_test_sha512_vectors | 4.822m | 9.117ms | 1 | 1 | 100.00 | ||
| hmac_test_hmac256_vectors | 8.090s | 265.688us | 1 | 1 | 100.00 | ||
| hmac_test_hmac384_vectors | 6.990s | 1.073ms | 1 | 1 | 100.00 | ||
| hmac_test_hmac512_vectors | 7.330s | 1.724ms | 1 | 1 | 100.00 | ||
| hmac_stress_all | 55.950s | 1.677ms | 1 | 1 | 100.00 | ||
| V2 | stress_all | hmac_stress_all | 55.950s | 1.677ms | 1 | 1 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.590s | 15.960us | 1 | 1 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | hmac_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| hmac_csr_rw | 0 | 1 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0 | 1 | 0.00 | ||
| hmac_csr_rw | 0 | 1 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 1 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 13 | 17 | 76.47 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.740s | 450.762us | 1 | 1 | 100.00 |
| hmac_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 3.220s | 372.603us | 1 | 1 | 100.00 |
| V3 | stress_reset | hmac_stress_reset | 28.567s | 0 | 1 | 0.00 | |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 3.333m | 5.856ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 2 | 50.00 | |||
| Unmapped tests | hmac_directed | 2.010s | 2.172ms | 1 | 1 | 100.00 | |
| TOTAL | 17 | 28 | 60.71 |
Job killed most likely because its dependent job failed. has 9 failures:
Test hmac_tl_errors has 1 failures.
Test hmac_tl_intg_err has 1 failures.
Test hmac_intr_test has 1 failures.
Test hmac_csr_hw_reset has 1 failures.
Test hmac_csr_rw has 1 failures.
... and 4 more tests.
Job returned non-zero exit code has 3 failures:
Test cover_reg_top has 1 failures.
cover_reg_top
Log /nightly/current_run/scratch/master/hmac-sim-vcs/cover_reg_top/build.log
recompiling module tb
All of 80 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 15.635 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test hmac_stress_reset has 1 failures.
0.hmac_stress_reset.114729473682769430022740817146153210022859497086206647818445986372163682044990
Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_stress_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test hmac_test_sha256_vectors has 1 failures.
0.hmac_test_sha256_vectors.101905413373513535872499134917289125355238749103689551393817931982660824149570
Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255