359e412| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 28.200s | 3.869ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 11.130s | 4.551ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 25.556us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.670s | 46.702us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 22.779s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.040s | 168.640us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.670s | 46.702us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 1.040s | 168.640us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 7 | 71.43 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0.630s | 62.291us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 5.353m | 33.255ms | 0 | 1 | 0.00 |
| V2 | host_maxperf | i2c_host_perf | 50.732m | 49.485ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.630s | 43.939us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 1.480m | 19.600ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 49.560s | 11.478ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.920s | 600.786us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 2.960s | 648.420us | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 5.810s | 667.760us | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 1.250m | 4.216ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 9.100s | 908.346us | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.120s | 82.337us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 2.040s | 542.395us | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 39.270s | 39.898ms | 1 | 1 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 2.290s | 477.578us | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 22.489s | 0 | 1 | 0.00 | |
| i2c_target_intr_smoke | 26.571s | 0 | 1 | 0.00 | |||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0.900s | 179.271us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 0.780s | 132.161us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 5.990s | 45.691ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 22.489s | 0 | 1 | 0.00 | |||
| i2c_target_intr_stress_wr | 20.810s | 22.744ms | 1 | 1 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 4.150s | 5.448ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 10.990s | 2.082ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 2.530s | 747.082us | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 19.776s | 0 | 1 | 0.00 | |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 0.750s | 77.710us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.120s | 544.192us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 50.732m | 49.485ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 21.551s | 0 | 1 | 0.00 | |||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 9.100s | 908.346us | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 1.440s | 135.220us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 2.110s | 1.132ms | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.960s | 1.791ms | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 1.050s | 583.548us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 4.780s | 876.556us | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.420s | 513.984us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.590s | 40.247us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.640s | 53.784us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 0.940s | 78.257us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 0.940s | 78.257us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 25.556us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.670s | 46.702us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.040s | 168.640us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 25.556us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.670s | 46.702us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.040s | 168.640us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 29 | 38 | 76.32 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.560s | 163.269us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0.830s | 390.695us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.560s | 163.269us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 2.190s | 152.946us | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.160s | 423.577us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 6.580s | 7.662ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 36 | 50 | 72.00 |
Job returned non-zero exit code has 5 failures:
Test i2c_host_perf_precise has 1 failures.
0.i2c_host_perf_precise.85599868359983113700784449187612817394252044130149415295340249757238073311121
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_perf_precise/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:21 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_stress_rd has 1 failures.
0.i2c_target_stress_rd.57821290397217863568101579368107924485797018378701820841687823124374323548005
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_rd/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:22 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_intr_smoke has 1 failures.
0.i2c_target_intr_smoke.59015062190583492247050336013791714535429060545871548222881224250662143154667
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_intr_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:22 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_hrst has 1 failures.
0.i2c_target_hrst.76017621415792756958203897070960099816635605782153393890873915606208668773796
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:22 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_csr_bit_bash has 1 failures.
0.i2c_csr_bit_bash.49626491100274797872059452838859215286680037135630986381498867525532865797723
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:25 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Job timed out after * minutes has 2 failures:
Test i2c_same_csr_outstanding has 1 failures.
0.i2c_same_csr_outstanding.82236284167501895332262017385168079710372465715743238796348802405243041198821
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
Job timed out after 60 minutes
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
0.i2c_csr_mem_rw_with_rand_reset.78509845822460652827972914116019634993489721956213541741602704965750480283837
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest/run.log
Job timed out after 60 minutes
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:
0.i2c_host_error_intr.93374188080449870409315299832224524801768030219660184285511523977234270933151
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 62290660 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 62290660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
0.i2c_host_stress_all.78540287364407784135656224374906429142213105885371371796841068701792106162593
Line 148, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 33254714685 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.47845720247239288523871379286525287533734984488277374527967299215030131779762
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 542395407 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 542395407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.111557776114600651189424740337163508101189247207921763862399091545004948973136
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 423576519 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 52 [0x34])
UVM_INFO @ 423576519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.i2c_host_stress_all_with_rand_reset.75386568757063700181375962486283064290696779978113895252571104944110152277002
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 152946138 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 152946138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
0.i2c_target_stress_all_with_rand_reset.96211245409053497498668507774819559176898162082593421944985697058481046189537
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7662291306 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7662291306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
0.i2c_host_mode_toggle.76049168594352709143937581444443560491567319813673349956254946151910078733546
Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 82337157 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------