KMAC/MASKED Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.370s	334.000us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.860s	113.446us	1	1	100.00
V1	csr_rw	kmac_csr_rw	15.984s		0	1	0.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.540s	1.418ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	2.900s	285.780us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.240s	84.268us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	15.984s		0	1	0.00
		kmac_csr_aliasing	2.900s	285.780us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.680s	34.928us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.960s	58.971us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	long_msg_and_output	kmac_long_msg_and_output	11.622m	10.573ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.252m	14.333ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.530s	8.933ms	1	1	100.00
		kmac_test_vectors_sha3_256	20.602m	72.632ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.860s	5.916ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.810s	1.681ms	1	1	100.00
		kmac_test_vectors_shake_128	2.396m	8.347ms	1	1	100.00
		kmac_test_vectors_shake_256	26.956m	174.805ms	1	1	100.00
		kmac_test_vectors_kmac	2.210s	383.160us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.960s	1.204ms	1	1	100.00
V2	sideload	kmac_sideload	1.844m	9.883ms	1	1	100.00
V2	app	kmac_app	3.681m	65.990ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.924m	7.140ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.372m	19.224ms	1	1	100.00
V2	error	kmac_error	2.147m	10.308ms	1	1	100.00
V2	key_error	kmac_key_error	4.700s	930.657us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.330s	222.657us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.480s	989.869us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	0.940s	43.500us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	40.780s	10.572ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.160s	37.587us	1	1	100.00
V2	stress_all	kmac_stress_all	20.264m	585.050ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.690s	14.180us	1	1	100.00
V2	alert_test	kmac_alert_test			0	1	0.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.390s	123.197us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.390s	123.197us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.860s	113.446us	1	1	100.00
		kmac_csr_rw	15.984s		0	1	0.00
		kmac_csr_aliasing	2.900s	285.780us	1	1	100.00
		kmac_same_csr_outstanding	1.090s	27.871us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.860s	113.446us	1	1	100.00
		kmac_csr_rw	15.984s		0	1	0.00
		kmac_csr_aliasing	2.900s	285.780us	1	1	100.00
		kmac_same_csr_outstanding	1.090s	27.871us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.090s	151.701us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.090s	151.701us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.090s	151.701us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.090s	151.701us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.800s	310.628us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.307m	14.213ms	1	1	100.00
		kmac_tl_intg_err	1.760s	77.945us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.760s	77.945us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.160s	37.587us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.370s	334.000us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.844m	9.883ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.090s	151.701us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.307m	14.213ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.307m	14.213ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.307m	14.213ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.370s	334.000us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.160s	37.587us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.307m	14.213ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.047m	8.389ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.370s	334.000us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	30.800s	7.744ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test kmac_alert_test has 1 failures.

    • 0.kmac_alert_test.23461513139979325547540485518827308852712644510388834799540335666548088776402
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_alert_test/latest/run.log

        Job timed out after 60 minutes
      

• Job returned non-zero exit code has 1 failures:

  • Test kmac_csr_rw has 1 failures.

    • 0.kmac_csr_rw.57145249040971553301272956227750674931320309614258913809139410490351915055988
      Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:21 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255