359e412| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.750s | 52.327us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 0.780s | 42.860us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 20.365s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | kmac_csr_aliasing | 2.880s | 299.731us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 1.820s | 739.455us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.780s | 42.860us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 2.880s | 299.731us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 24.871s | 0 | 1 | 0.00 | |
| V1 | mem_partial_access | kmac_mem_partial_access | 0.910s | 35.973us | 1 | 1 | 100.00 |
| V1 | TOTAL | 5 | 8 | 62.50 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0 | 1 | 0.00 | ||
| V2 | burst_write | kmac_burst_write | 0 | 1 | 0.00 | ||
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0 | 1 | 0.00 | ||
| kmac_test_vectors_sha3_256 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_sha3_384 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_sha3_512 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_shake_128 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_shake_256 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_kmac | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_kmac_xof | 0 | 1 | 0.00 | ||||
| V2 | sideload | kmac_sideload | 0 | 1 | 0.00 | ||
| V2 | app | kmac_app | 0 | 1 | 0.00 | ||
| V2 | app_with_partial_data | kmac_app_with_partial_data | 0 | 1 | 0.00 | ||
| V2 | entropy_refresh | kmac_entropy_refresh | 0 | 1 | 0.00 | ||
| V2 | error | kmac_error | 0 | 1 | 0.00 | ||
| V2 | key_error | kmac_key_error | 0 | 1 | 0.00 | ||
| V2 | sideload_invalid | kmac_sideload_invalid | 0 | 1 | 0.00 | ||
| V2 | edn_timeout_error | kmac_edn_timeout_error | 0 | 1 | 0.00 | ||
| V2 | entropy_mode_error | kmac_entropy_mode_error | 0 | 1 | 0.00 | ||
| V2 | entropy_ready_error | kmac_entropy_ready_error | 0 | 1 | 0.00 | ||
| V2 | lc_escalation | kmac_lc_escalation | 0 | 1 | 0.00 | ||
| V2 | stress_all | kmac_stress_all | 0 | 1 | 0.00 | ||
| V2 | intr_test | kmac_intr_test | 20.455s | 0 | 1 | 0.00 | |
| V2 | alert_test | kmac_alert_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 1.990s | 50.894us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 1.990s | 50.894us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.750s | 52.327us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.780s | 42.860us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 2.880s | 299.731us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.760s | 175.723us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.750s | 52.327us | 1 | 1 | 100.00 |
| kmac_csr_rw | 0.780s | 42.860us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 2.880s | 299.731us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.760s | 175.723us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 2 | 26 | 7.69 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.100s | 39.396us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.100s | 39.396us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.100s | 39.396us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.100s | 39.396us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 1.830s | 54.479us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 0 | 1 | 0.00 | ||
| kmac_tl_intg_err | 2.650s | 106.221us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 2.650s | 106.221us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0 | 1 | 0.00 | ||
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_key_sideload | kmac_sideload | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.100s | 39.396us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0 | 1 | 0.00 | ||
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 0 | 1 | 0.00 | ||
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 0 | 1 | 0.00 | ||
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 3 | 5 | 60.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 10 | 40 | 25.00 |
Job killed most likely because its dependent job failed. has 27 failures:
Test kmac_smoke has 1 failures.
Test kmac_long_msg_and_output has 1 failures.
Test kmac_sideload has 1 failures.
Test kmac_sideload_invalid has 1 failures.
Test kmac_burst_write has 1 failures.
... and 22 more tests.
Job returned non-zero exit code has 4 failures:
Test default has 1 failures.
default
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/build.log
recompiling module tb
All of 118 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 20.339 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test kmac_mem_walk has 1 failures.
0.kmac_mem_walk.102732310069347976563867768092081531218021822544221982089433808887440333782561
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_intr_test has 1 failures.
0.kmac_intr_test.89305225701750391187132813711078358550062480128774809043837793892563496486288
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_csr_bit_bash has 1 failures.
0.kmac_csr_bit_bash.13024815430488306933454335983300721021859898694031927986999975649479322610200
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 22 16:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255