ROM_CTRL/32KB Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.820s	1.019ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.190s	302.858us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.450s	280.371us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.070s	385.150us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.010s	207.066us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	3.760s	309.605us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.450s	280.371us	1	1	100.00
		rom_ctrl_csr_aliasing	3.010s	207.066us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.290s	581.660us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.210s	123.811us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.620s	415.364us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	18.354s		0	1	0.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.230s	298.183us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.000s	213.074us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	4.650s	129.141us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	4.650s	129.141us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.190s	302.858us	1	1	100.00
		rom_ctrl_csr_rw	3.450s	280.371us	1	1	100.00
		rom_ctrl_csr_aliasing	3.010s	207.066us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.270s	2.245ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.190s	302.858us	1	1	100.00
		rom_ctrl_csr_rw	3.450s	280.371us	1	1	100.00
		rom_ctrl_csr_aliasing	3.010s	207.066us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.270s	2.245ms	1	1	100.00
V2		TOTAL			5	6	83.33
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	10.270s	2.587ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.138m	950.172us	0	1	0.00
		rom_ctrl_tl_intg_err	21.050s	192.122us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.138m	950.172us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.138m	950.172us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.138m	950.172us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.138m	950.172us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.820s	1.019ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.820s	1.019ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.820s	1.019ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	21.050s	192.122us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
		rom_ctrl_kmac_err_chk	7.230s	298.183us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.030s	431.402us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	10.270s	2.587ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.138m	950.172us	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.588m	3.384ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	19	84.21

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 0.rom_ctrl_stress_all.113546572438293745315973712755945214796663484120545754500740673577610145240123
      Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.41497153616567627325210130957147644614537500285075989798071308594443127682333
      Line 85, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 431401642 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 431401642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.90611058159253791422912291965352866795259351015111500282694629288203575304240
      Line 302, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 39132915ps failed at 39132915ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 43102882ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 43102882ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))