RV_TIMER Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: `359e412`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.650s	180.968us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.580s	51.049us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	22.727s		0	1	0.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.690s	64.951us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.650s	24.855us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.650s	26.764us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	22.727s		0	1	0.00
		rv_timer_csr_aliasing	0.650s	24.855us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	random_reset	rv_timer_random_reset	1.020s	111.471us	0	1	0.00
V2	disabled	rv_timer_disabled	0.910s	3.555ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.885m	294.266ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.885m	294.266ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.210s	6.802ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.530s	37.709us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.510s	18.245us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.810s	95.154us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.810s	95.154us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.580s	51.049us	1	1	100.00
		rv_timer_csr_rw	22.727s		0	1	0.00
		rv_timer_csr_aliasing	0.650s	24.855us	1	1	100.00
		rv_timer_same_csr_outstanding	0.570s	14.108us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.580s	51.049us	1	1	100.00
		rv_timer_csr_rw	22.727s		0	1	0.00
		rv_timer_csr_aliasing	0.650s	24.855us	1	1	100.00
		rv_timer_same_csr_outstanding	0.570s	14.108us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.680s	267.807us	1	1	100.00
		rv_timer_tl_intg_err	0.720s	642.270us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.720s	642.270us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.570s	127.914us	0	1	0.00
V3	max_value	rv_timer_max	1.360s	42.760us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	16.480s	3.143ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			14	19	73.68

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
- Test rv_timer_min has 1 failures.
  - 0.rv_timer_min.104830341509700693864553540102129873968566031218579738484100605308496607865708
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 127913623 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf319c504) == 0x1
  UVM_INFO @ 127913623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_random_reset has 1 failures.
  - 0.rv_timer_random_reset.58936894753321642689179337337949010662825255415838196824935831508111048592345
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 111471395 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x84ac1504) == 0x1
  UVM_INFO @ 111471395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 0.rv_timer_max.71447636947381518626091278211058871501378850682130451041890645920842044488355
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  42759998 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @  42759998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 0.rv_timer_stress_all_with_rand_reset.2216914271022482086225972120275597964075174948009757164466338060010953745519
    Line 313, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3142699439 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 3142699439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test rv_timer_csr_rw has 1 failures.

0.rv_timer_csr_rw.97681705592001892808112409520327026400427696751367508440725612569699688966891
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest/run.log

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  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255