SPI_DEVICE/1R1W Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	28.520s	4.839ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.750s	40.610us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	11.992s		0	1	0.00
V1	csr_bit_bash	spi_device_csr_bit_bash	7.720s	181.635us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.360s	3.415ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.810s	134.502us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	11.992s		0	1	0.00
		spi_device_csr_aliasing	10.360s	3.415ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.630s	41.469us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.590s	330.963us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	csb_read	spi_device_csb_read	0.740s	21.722us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.620s	5.576us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	5.807us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.080s	395.431us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.080s	395.431us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.840s	2.983ms	1	1	100.00
		spi_device_tpm_sts_read	0.670s	33.232us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.430s	1.227ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	18.450s	18.909ms	1	1	100.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.550s	77.190us	1	1	100.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.550s	77.190us	1	1	100.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	30.535s		0	1	0.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	30.535s		0	1	0.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.535s		0	1	0.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	30.535s		0	1	0.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.535s		0	1	0.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.500s	1.239ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.680s	338.409us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.680s	338.409us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.680s	338.409us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.420s	331.851us	1	1	100.00
		spi_device_read_buffer_direct	7.440s	1.507ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.680s	338.409us	1	1	100.00
		spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.434m	197.552ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.170s	1.653ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.170s	1.653ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	28.520s	4.839ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.434m	33.218ms	1	1	100.00
V2	stress_all	spi_device_stress_all	46.500s	4.300ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.630s	14.035us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.660s	23.570us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.200s	53.771us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.200s	53.771us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.750s	40.610us	1	1	100.00
		spi_device_csr_rw	11.992s		0	1	0.00
		spi_device_csr_aliasing	10.360s	3.415ms	1	1	100.00
		spi_device_same_csr_outstanding	1.440s	390.265us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.750s	40.610us	1	1	100.00
		spi_device_csr_rw	11.992s		0	1	0.00
		spi_device_csr_aliasing	10.360s	3.415ms	1	1	100.00
		spi_device_same_csr_outstanding	1.440s	390.265us	1	1	100.00
V2		TOTAL			19	22	86.36
V2S	tl_intg_err	spi_device_sec_cm	0.910s	256.456us	1	1	100.00
		spi_device_tl_intg_err	9.850s	579.657us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.850s	579.657us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.227m	9.870ms	1	1	100.00
		TOTAL			29	33	87.88

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test spi_device_intercept has 1 failures.

    • 0.spi_device_intercept.68362306457593048667502910118262866772158991458309188051734112218542372137941
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:23 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test spi_device_csr_rw has 1 failures.

    • 0.spi_device_csr_rw.20198378350227285971877799513109057603513854026736485804277208789642363427410
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:26 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.40632600281667934810922515170835396436392047987983352469535532014972721852945
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4825982 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[53])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4825982 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4825982 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[949])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.88862804447903181857834976757245178139654488451165193333462632580686558622913
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3471660 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x64dd47 [11001001101110101000111] vs 0x0 [0])
        UVM_ERROR @   3512660 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x25f078 [1001011111000001111000] vs 0x0 [0])
        UVM_ERROR @   3518660 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xac1dca [101011000001110111001010] vs 0x0 [0])
        UVM_ERROR @   3561660 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x780966 [11110000000100101100110] vs 0x0 [0])
        UVM_ERROR @   3626660 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe79cea [111001111001110011101010] vs 0x0 [0])