SRAM_CTRL/MAIN Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	46.720s	11.391ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	12.986us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.640s	47.523us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.120s	94.757us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.660s	23.285us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.430s	1.470ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.640s	47.523us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	23.285us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.921m	20.712ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.699m	10.046ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.123m	45.919ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.365m	9.379ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.767m	407.045ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.691m	71.366ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	30.787s		0	1	0.00
V2	executable	sram_ctrl_executable	1.737m	7.354ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.940s	5.231ms	1	1	100.00
		sram_ctrl_partial_access_b2b	18.117s		0	1	0.00
V2	max_throughput	sram_ctrl_max_throughput	25.350s	3.056ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	22.120s	1.821ms	1	1	100.00
		sram_ctrl_throughput_w_readback	13.560s	3.259ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.197m	2.950ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.070s	1.400ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	28.423m	155.201ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.650s	23.915us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.730s	61.124us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.730s	61.124us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	12.986us	1	1	100.00
		sram_ctrl_csr_rw	0.640s	47.523us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	23.285us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	121.176us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	12.986us	1	1	100.00
		sram_ctrl_csr_rw	0.640s	47.523us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	23.285us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	121.176us	1	1	100.00
V2		TOTAL			15	17	88.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	13.631s		0	1	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.580s	2.510us	0	1	0.00
		sram_ctrl_tl_intg_err	1.710s	404.052us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.580s	2.510us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.710s	404.052us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.197m	2.950ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.197m	2.950ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.640s	47.523us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.737m	7.354ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.737m	7.354ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.737m	7.354ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	30.787s		0	1	0.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.520s	709.208us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	13.631s		0	1	0.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.230s	2.474ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	46.720s	11.391ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	46.720s	11.391ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.737m	7.354ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.580s	2.510us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	30.787s		0	1	0.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.580s	2.510us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.580s	2.510us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	46.720s	11.391ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.580s	2.510us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.680s	2.541ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test sram_ctrl_partial_access_b2b has 1 failures.

    • 0.sram_ctrl_partial_access_b2b.50916367149865683569760463212968458489419966539480353887354375649576698327063
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_lc_escalation has 1 failures.

    • 0.sram_ctrl_lc_escalation.73384086926421011461477119607847746649800702210165248584876560812691551788496
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

    • 0.sram_ctrl_passthru_mem_tl_intg_err.14950852058129217629796817715047344943579509164479727023653380111755252252631
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:22 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.20201725022249602355157711541275962522259293466319451189567147527549836530570
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 1754600ps failed at 1754600ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 1765017ps failed at 1765017ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'