SRAM_CTRL/RET Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.210s	41.994us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.660s	53.524us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.600s	22.633us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.320s	42.468us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.610s	72.385us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.290s	125.665us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.600s	22.633us	1	1	100.00
		sram_ctrl_csr_aliasing	0.610s	72.385us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.210s	79.697us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	16.408s		0	1	0.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	3.663m	17.691ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	17.950s		0	1	0.00
V2	bijection	sram_ctrl_bijection	54.820s	20.016ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.611m	2.431ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.060s	447.207us	1	1	100.00
V2	executable	sram_ctrl_executable	45.810s	1.649ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.310s	76.686us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.870m	12.802ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	35.800s	545.315us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.610s	62.057us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.080s	172.247us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.351s		0	1	0.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.660s	79.686us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	4.127m	13.252ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.610s	69.127us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.900s	314.873us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.900s	314.873us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.660s	53.524us	1	1	100.00
		sram_ctrl_csr_rw	0.600s	22.633us	1	1	100.00
		sram_ctrl_csr_aliasing	0.610s	72.385us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	40.562us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.660s	53.524us	1	1	100.00
		sram_ctrl_csr_rw	0.600s	22.633us	1	1	100.00
		sram_ctrl_csr_aliasing	0.610s	72.385us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	40.562us	1	1	100.00
V2		TOTAL			15	17	88.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.280s	590.723us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.680s	13.042us	0	1	0.00
		sram_ctrl_tl_intg_err	1.190s	216.842us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.680s	13.042us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.190s	216.842us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.351s		0	1	0.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.351s		0	1	0.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.600s	22.633us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	45.810s	1.649ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	45.810s	1.649ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	45.810s	1.649ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.060s	447.207us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.760s	34.468us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.280s	590.723us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.800s	32.332us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.210s	41.994us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.210s	41.994us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	45.810s	1.649ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.680s	13.042us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.060s	447.207us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.680s	13.042us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.680s	13.042us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.210s	41.994us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.680s	13.042us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.111m	2.004ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	31	87.10

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test sram_ctrl_stress_pipeline has 1 failures.

    • 0.sram_ctrl_stress_pipeline.26965598948172708592040978560520490118540644532596515086344255890333261236210
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:12 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_regwen has 1 failures.

    • 0.sram_ctrl_regwen.45068265363901484942259588656786849514617588404398813681950856648495339909580
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:12 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test sram_ctrl_mem_partial_access has 1 failures.

    • 0.sram_ctrl_mem_partial_access.91474061006001307797997079222637517091874206012326384457037513477040569342835
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:12 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.20403885438824968065286157933617622790771492380780757803506627595863535072338
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  13042041 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  13042041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---