CHIP Simulation Results

Monday September 22 2025 16:09:37 UTC

GitHub Revision: 359e412

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	10.367s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	10.367s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	10.370s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.438s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	14.087s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.419s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.419s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.419s		0	1	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	10.894s		0	1	0.00
		chip_sw_example_manufacturer	14.894s		0	1	0.00
		chip_sw_example_concurrency	12.156s		0	1	0.00
		chip_sw_uart_smoketest_signed	49.401s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	7.900s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	14.138s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.138s		0	1	0.00
V1	xbar_smoke	xbar_smoke			0	1	0.00
V1		TOTAL			0	12	0.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	10.422s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.248s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.724s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.386s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.386s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.731s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.282s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	28.476s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	28.476s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.444s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	10.416s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.378s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.378s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	28.523s		0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.131m	3.312ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	14.380s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	14.637s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	14.207s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	15.748m	25.483ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	13.777s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	16.564s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	16.564s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	16.496s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.704s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.704s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	17.047s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	14.828s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.443s		0	1	0.00
		chip_sw_aes_idle	14.795s		0	1	0.00
		chip_sw_hmac_enc_idle	14.842s		0	1	0.00
		chip_sw_kmac_idle	14.361s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.407s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.823s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.235s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.237s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.300s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.538s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.794s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.562s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.240s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.300s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.538s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.794s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.562s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.771s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.188s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	15.070s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.366s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	14.306s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.586s		0	1	0.00
		chip_sw_clkmgr_jitter	14.919s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	16.240s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.509s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	15.954s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	15.840s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	16.223s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	15.719s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	16.165s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.314s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	14.327s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.992s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	14.448s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	12.460s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.360s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	16.704s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	16.656s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.360s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.904s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.367s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.445s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.903s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.340s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	12.460s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	14.380s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.356s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	15.052s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.917s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	15.221s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	12.460s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.909s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.794s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	12.460s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.383s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.917s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.037s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.975s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.618s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.216s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.685s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.385s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.794s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	10.509s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	14.368s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.403s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.356s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.402s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	10.301s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	14.372s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	14.590s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	14.880s		0	1	0.00
		chip_prim_tl_access	5.846m	14.160ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.240s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.300s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.538s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.794s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.562s		0	1	0.00
		chip_rv_dm_lc_disabled	15.748m	25.483ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	15.402s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.188s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	14.622s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	14.795s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	14.780s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	15.070s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	14.842s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	14.191s		0	1	0.00
		chip_sw_kmac_mode_kmac	14.364s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	14.306s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	14.372s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	14.537s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	10.363s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	14.361s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.325s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.325s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.143s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	14.141s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.142s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	14.372s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.366s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.928s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	15.771s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	16.443s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	16.443s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	16.443s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	15.719s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	14.590s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	14.590s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	14.241s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.586s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	14.880s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	12.460s		0	1	0.00
		chip_sw_data_integrity_escalation	13.378s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	15.719s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	14.372s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	14.241s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	15.951s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	15.719s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	14.372s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	14.241s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	15.951s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.452s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	10.509s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.403s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.356s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.402s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	10.301s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.535s		0	1	0.00
		chip_prim_tl_access	5.846m	14.160ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.846m	14.160ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.999s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.413s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	14.327s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	15.771s		0	1	0.00
		chip_sw_aes_enc_jitter_en	15.188s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	15.070s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.366s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	14.306s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.586s		0	1	0.00
		chip_sw_clkmgr_jitter	14.919s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	14.367s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	14.367s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	14.316s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	14.526s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	16.850s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	15.811s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	15.327s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	14.396s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	15.951s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	14.356s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	14.356s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	47.794s		0	1	0.00
		chip_sw_aon_timer_smoketest	48.199s		0	1	0.00
		chip_sw_clkmgr_smoketest	47.783s		0	1	0.00
		chip_sw_csrng_smoketest	48.345s		0	1	0.00
		chip_sw_gpio_smoketest	41.916s		0	1	0.00
		chip_sw_hmac_smoketest	40.245s		0	1	0.00
		chip_sw_kmac_smoketest	39.575s		0	1	0.00
		chip_sw_otbn_smoketest	37.815s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	38.020s		0	1	0.00
		chip_sw_rv_plic_smoketest	38.325s		0	1	0.00
		chip_sw_rv_timer_smoketest	39.196s		0	1	0.00
		chip_sw_rstmgr_smoketest	37.651s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	31.642s		0	1	0.00
		chip_sw_uart_smoketest	10.435s		0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	48.983s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	49.401s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	10.422s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.182s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	14.364s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	14.685s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	14.796s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	13.414s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	14.500s		0	1	0.00
		chip_rv_dm_lc_disabled	15.748m	25.483ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.269s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.607s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.484s		0	1	0.00
		chip_sw_lc_walkthrough_rma	10.606s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	14.500s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	10.949s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.957s		0	1	0.00
		rom_volatile_raw_unlock	10.374s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.320s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	10.474s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	10.419s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.138s		0	1	0.00
		chip_same_csr_outstanding	7.640s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.138s		0	1	0.00
		chip_same_csr_outstanding	7.640s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random			0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	1	0.00
		xbar_smoke_large_delays			0	1	0.00
		xbar_smoke_slow_rsp			0	1	0.00
		xbar_random_zero_delays			0	1	0.00
		xbar_random_large_delays			0	1	0.00
		xbar_random_slow_rsp			0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	1	0.00
		xbar_error_and_unmapped_addr			0	1	0.00
V2	xbar_error_cases	xbar_error_random			0	1	0.00
		xbar_error_and_unmapped_addr			0	1	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	1	0.00
		xbar_access_same_device_slow_rsp			0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	1	0.00
V2	xbar_stress_all	xbar_stress_all			0	1	0.00
		xbar_stress_all_with_error			0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	1	0.00
		xbar_stress_all_with_reset_error			0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.291s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.478s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.500s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.452s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.334s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	26.486s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	26.366s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	26.643s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.017s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.370s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	25.868s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.887s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.086s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	24.516s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.196s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.769s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.776s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.608s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.179s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.806s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.708s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.915s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	19.350s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.908s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.526s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.161s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.036s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.473s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.936s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.895s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.986s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.052s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	18.219s		0	1	0.00
		rom_e2e_asm_init_dev	18.219s		0	1	0.00
		rom_e2e_asm_init_prod	17.835s		0	1	0.00
		rom_e2e_asm_init_prod_end	10.378s		0	1	0.00
		rom_e2e_asm_init_rma	10.382s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.532s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.531s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.534s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.481s		0	1	0.00
V2		TOTAL			2	205	0.98
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	14.505s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	14.272s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.434s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.434s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.381s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.330s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	12.460s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	14.467s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.316s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	15.117s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.873s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.434s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.434s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.381s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.488s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.372s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.430s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	39.176s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	13.068s		0	1	0.00
		chip_sw_entropy_src_kat_test	14.538s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	15.122s		0	1	0.00
		chip_plic_all_irqs_0	14.823s		0	1	0.00
		chip_plic_all_irqs_10	14.829s		0	1	0.00
		chip_sw_dma_inline_hashing	15.750s		0	1	0.00
		chip_sw_dma_abort	15.298s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.367s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.323s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.370s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.493s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.337s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.543s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.276s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.484s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.482s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.377s		0	1	0.00
		chip_sw_entropy_src_smoketest	44.983s		0	1	0.00
		chip_sw_mbx_smoketest	38.849s		0	1	0.00
		TOTAL			2	250	0.80

Failure Buckets

• Job returned non-zero exit code has 226 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.81462190210153595490116887598383695417442280679252457166723991336859257674738
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 22 16:27 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.112878365103153463286420123284692754510399805093771941993115526171884243807153
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

                    done; \
                fi; \
            fi; \
        done;
        Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
        Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_rom_sim_dv
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/bazel_skylib/1.7.1/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

  • Test chip_sw_example_manufacturer has 1 failures.

    • 0.chip_sw_example_manufacturer.54323875634785636279905992091555691472912731726559404995862962211884540089374
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp10424541836215371293/20250217_01.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp10424541836215371293/20250217_01.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_example_concurrency has 1 failures.

    • 0.chip_sw_example_concurrency.80465621878932513831191341159627309908390169028777405834291168525483174517754
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp16728471727625466639/20250217_01.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp16728471727625466639/20250217_01.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 0.chip_sw_all_escalation_resets.108116858685757716320206670335662175800060710399863728207321748280432824875573
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

          <builtin>: in <toplevel>
        Repository rule http_archive defined at:
          /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'rules_multitool+':
           Traceback (most recent call last):
            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp13946664148506099766/temp-fork-0.4.tar.gz: Unknown host: github.com
        ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_multitool+/temp13946664148506099766/temp-fork-0.4.tar.gz: Unknown host: github.com
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37
      

  • ... and 221 more tests.

• Job killed most likely because its dependent job failed. has 18 failures:

  • Test xbar_smoke has 1 failures.

    • 0.xbar_smoke.62635952262478759042415804648434009775229588151525272725891306023879557884875
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest/run.log

  • Test xbar_smoke_zero_delays has 1 failures.

    • 0.xbar_smoke_zero_delays.27251137824292729350595073194308489206384149353914497150882637331051590605282
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log

  • Test xbar_smoke_large_delays has 1 failures.

    • 0.xbar_smoke_large_delays.21537260097152409285253626394385980915500837992235118916209815578513713012571
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log

  • Test xbar_smoke_slow_rsp has 1 failures.

    • 0.xbar_smoke_slow_rsp.88592554511359007441311030192219697355959433749493845022426231673407709062804
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log

  • Test xbar_random has 1 failures.

    • 0.xbar_random.31008934220683207585275433197113286298470478183745532870959825963878508731029
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_random/latest/run.log

  • ... and 13 more tests.

• Job timed out after * minutes has 2 failures:

  • Test xbar_build_mode has 1 failures.

    • xbar_build_mode
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/xbar_build_mode/build.log

        Job timed out after 60 minutes
      

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.47719116204653124358675797289693690393888394318663419669058811171850493946298
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 2 failures:

  • Test chip_csr_bit_bash has 1 failures.

    • 0.chip_csr_bit_bash.81976576493256664531494270643525191622706424147063991304822693556271187508482
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.6084585094189530950798540099099083574552556870394395712403506543321566163576
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_jtag_mem_access has 1 failures.

    • 0.chip_jtag_mem_access.24558027440446664300826072200215989829495957570393163400164959057352175645747
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 3312.446650 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'he6302013  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h0  a_user: 'h26959  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3312.446650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---