DMA Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 dma_memory_smoke dma_memory_smoke 29.000s 0 1 0.00
V1 dma_handshake_smoke dma_handshake_smoke 30.000s 0 1 0.00
V1 dma_generic_smoke dma_generic_smoke 4.000s 1.551ms 1 1 100.00
V1 csr_hw_reset dma_csr_hw_reset 29.000s 0 1 0.00
V1 csr_rw dma_csr_rw 17.000s 0 1 0.00
V1 csr_bit_bash dma_csr_bit_bash 30.000s 0 1 0.00
V1 csr_aliasing dma_csr_aliasing 18.000s 0 1 0.00
V1 csr_mem_rw_with_rand_reset dma_csr_mem_rw_with_rand_reset 39.000s 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr dma_csr_rw 17.000s 0 1 0.00
dma_csr_aliasing 18.000s 0 1 0.00
V1 TOTAL 1 8 12.50
V2 dma_memory_region_lock dma_memory_region_lock 25.000s 0 1 0.00
V2 dma_memory_tl_error dma_memory_stress 37.000s 0 1 0.00
V2 dma_handshake_tl_error dma_handshake_stress 3.850m 21.910ms 1 1 100.00
V2 dma_handshake_stress dma_handshake_stress 3.850m 21.910ms 1 1 100.00
V2 dma_memory_stress dma_memory_stress 37.000s 0 1 0.00
V2 dma_generic_stress dma_generic_stress 21.000s 0 1 0.00
V2 dma_handshake_mem_buffer_overflow dma_handshake_stress 3.850m 21.910ms 1 1 100.00
V2 dma_abort dma_abort 25.000s 0 1 0.00
V2 dma_stress_all dma_stress_all 26.000s 0 1 0.00
V2 alert_test dma_alert_test 29.000s 0 1 0.00
V2 intr_test dma_intr_test 30.000s 0 1 0.00
V2 tl_d_oob_addr_access dma_tl_errors 41.000s 0 1 0.00
V2 tl_d_illegal_access dma_tl_errors 41.000s 0 1 0.00
V2 tl_d_outstanding_access dma_csr_hw_reset 29.000s 0 1 0.00
dma_csr_rw 17.000s 0 1 0.00
dma_csr_aliasing 18.000s 0 1 0.00
dma_same_csr_outstanding 34.000s 0 1 0.00
V2 tl_d_partial_access dma_csr_hw_reset 29.000s 0 1 0.00
dma_csr_rw 17.000s 0 1 0.00
dma_csr_aliasing 18.000s 0 1 0.00
dma_same_csr_outstanding 34.000s 0 1 0.00
V2 TOTAL 1 10 10.00
V2S dma_illegal_addr_range dma_mem_enabled 25.000s 0 1 0.00
dma_generic_stress 21.000s 0 1 0.00
dma_handshake_stress 3.850m 21.910ms 1 1 100.00
V2S dma_config_lock dma_config_lock 29.000s 0 1 0.00
V2S tl_intg_err dma_tl_intg_err 2.000s 113.770us 1 1 100.00
dma_sec_cm 25.000s 0 1 0.00
V2S TOTAL 1 4 25.00
Unmapped tests dma_short_transfer 29.000s 0 1 0.00
dma_longer_transfer 29.000s 0 1 0.00
dma_stress_all_with_rand_reset 21.000s 0 1 0.00
TOTAL 3 25 12.00

Failure Buckets