EDN Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.830s	37.390us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.730s	22.959us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.800s	16.796us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.170s	111.596us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.000s	50.403us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	24.557s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.800s	16.796us	1	1	100.00
		edn_csr_aliasing	1.000s	50.403us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	firmware	edn_genbits	1.060s	61.275us	1	1	100.00
V2	csrng_commands	edn_genbits	1.060s	61.275us	1	1	100.00
V2	genbits	edn_genbits	1.060s	61.275us	1	1	100.00
V2	interrupts	edn_intr	0.800s	38.695us	1	1	100.00
V2	alerts	edn_alert	0.940s	26.608us	1	1	100.00
V2	errs	edn_err	0.760s	22.167us	1	1	100.00
V2	disable	edn_disable	0.740s	13.375us	1	1	100.00
		edn_disable_auto_req_mode	1.010s	37.362us	1	1	100.00
V2	stress_all	edn_stress_all	2.330s	284.615us	1	1	100.00
V2	intr_test	edn_intr_test	0.680s	20.973us	1	1	100.00
V2	alert_test	edn_alert_test	0.750s	28.156us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.210s	89.374us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.210s	89.374us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.730s	22.959us	1	1	100.00
		edn_csr_rw	0.800s	16.796us	1	1	100.00
		edn_csr_aliasing	1.000s	50.403us	1	1	100.00
		edn_same_csr_outstanding	0.910s	72.052us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.730s	22.959us	1	1	100.00
		edn_csr_rw	0.800s	16.796us	1	1	100.00
		edn_csr_aliasing	1.000s	50.403us	1	1	100.00
		edn_same_csr_outstanding	0.910s	72.052us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.410s	566.516us	1	1	100.00
		edn_tl_intg_err	1.380s	55.135us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.830s	21.131us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.940s	26.608us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.410s	566.516us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.410s	566.516us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.410s	566.516us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.410s	566.516us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.940s	26.608us	1	1	100.00
		edn_sec_cm	3.410s	566.516us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.940s	26.608us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.380s	55.135us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	22.337s		0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			19	21	90.48

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.60955764793315826124468522453674726922333741705390630845205116697212139556703
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test edn_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.edn_csr_mem_rw_with_rand_reset.102847830733668539971434152943861993991892037731813874781052971196796770878759
      Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:13 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255