HMAC Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	1.920s	1.632ms	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.660s	14.825us	1	1	100.00
V1	csr_rw	hmac_csr_rw	0.800s	19.343us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	3.770s	1.488ms	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.100s	158.640us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.360s	314.995us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.800s	19.343us	1	1	100.00
		hmac_csr_aliasing	5.100s	158.640us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	49.010s	4.608ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	4.960s	2.276ms	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	6.970s	149.009us	1	1	100.00
		hmac_test_sha384_vectors	6.793m	28.323ms	1	1	100.00
		hmac_test_sha512_vectors	6.255m	13.865ms	1	1	100.00
		hmac_test_hmac256_vectors	6.750s	952.426us	1	1	100.00
		hmac_test_hmac384_vectors	6.220s	1.762ms	1	1	100.00
		hmac_test_hmac512_vectors	6.770s	869.166us	1	1	100.00
V2	burst_wr	hmac_burst_wr	12.460s	360.570us	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	2.021m	5.473ms	1	1	100.00
V2	error	hmac_error	1.067m	7.034ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	2.890s	884.670us	1	1	100.00
V2	save_and_restore	hmac_smoke	1.920s	1.632ms	1	1	100.00
		hmac_long_msg	49.010s	4.608ms	1	1	100.00
		hmac_back_pressure	4.960s	2.276ms	1	1	100.00
		hmac_datapath_stress	2.021m	5.473ms	1	1	100.00
		hmac_burst_wr	12.460s	360.570us	1	1	100.00
		hmac_stress_all	25.167s		0	1	0.00
V2	fifo_empty_status_interrupt	hmac_smoke	1.920s	1.632ms	1	1	100.00
		hmac_long_msg	49.010s	4.608ms	1	1	100.00
		hmac_back_pressure	4.960s	2.276ms	1	1	100.00
		hmac_datapath_stress	2.021m	5.473ms	1	1	100.00
		hmac_wipe_secret	2.890s	884.670us	1	1	100.00
		hmac_test_sha256_vectors	6.970s	149.009us	1	1	100.00
		hmac_test_sha384_vectors	6.793m	28.323ms	1	1	100.00
		hmac_test_sha512_vectors	6.255m	13.865ms	1	1	100.00
		hmac_test_hmac256_vectors	6.750s	952.426us	1	1	100.00
		hmac_test_hmac384_vectors	6.220s	1.762ms	1	1	100.00
		hmac_test_hmac512_vectors	6.770s	869.166us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	1.920s	1.632ms	1	1	100.00
		hmac_long_msg	49.010s	4.608ms	1	1	100.00
		hmac_back_pressure	4.960s	2.276ms	1	1	100.00
		hmac_datapath_stress	2.021m	5.473ms	1	1	100.00
		hmac_burst_wr	12.460s	360.570us	1	1	100.00
		hmac_error	1.067m	7.034ms	1	1	100.00
		hmac_wipe_secret	2.890s	884.670us	1	1	100.00
		hmac_test_sha256_vectors	6.970s	149.009us	1	1	100.00
		hmac_test_sha384_vectors	6.793m	28.323ms	1	1	100.00
		hmac_test_sha512_vectors	6.255m	13.865ms	1	1	100.00
		hmac_test_hmac256_vectors	6.750s	952.426us	1	1	100.00
		hmac_test_hmac384_vectors	6.220s	1.762ms	1	1	100.00
		hmac_test_hmac512_vectors	6.770s	869.166us	1	1	100.00
		hmac_stress_all	25.167s		0	1	0.00
V2	stress_all	hmac_stress_all	25.167s		0	1	0.00
V2	alert_test	hmac_alert_test	0.550s	31.053us	1	1	100.00
V2	intr_test	hmac_intr_test	0.540s	42.804us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.590s	349.061us	1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.590s	349.061us	1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.660s	14.825us	1	1	100.00
		hmac_csr_rw	0.800s	19.343us	1	1	100.00
		hmac_csr_aliasing	5.100s	158.640us	1	1	100.00
		hmac_same_csr_outstanding	0.910s	45.177us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.660s	14.825us	1	1	100.00
		hmac_csr_rw	0.800s	19.343us	1	1	100.00
		hmac_csr_aliasing	5.100s	158.640us	1	1	100.00
		hmac_same_csr_outstanding	0.910s	45.177us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	tl_intg_err	hmac_sec_cm	0.750s	209.824us	1	1	100.00
		hmac_tl_intg_err	2.190s	1.164ms	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.190s	1.164ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	1.920s	1.632ms	1	1	100.00
V3	stress_reset	hmac_stress_reset	1.260s	69.395us	1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.674m	4.440ms	1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.910s	151.860us	1	1	100.00
		TOTAL			27	28	96.43

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test hmac_stress_all has 1 failures.

    • 0.hmac_stress_all.93078435612644878972203230393480148406164237897186416809870357943823781853094
      Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:13 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255