4330c70| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 0 | 1 | 0.00 | ||
| V1 | target_smoke | i2c_target_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | i2c_csr_hw_reset | 20.594s | 0 | 1 | 0.00 | |
| V1 | csr_rw | i2c_csr_rw | 24.777s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 1.940s | 377.715us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.050s | 137.428us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.840s | 63.528us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 24.777s | 0 | 1 | 0.00 | |
| i2c_csr_aliasing | 1.050s | 137.428us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 3 | 7 | 42.86 | |||
| V2 | host_error_intr | i2c_host_error_intr | 0 | 1 | 0.00 | ||
| V2 | host_stress_all | i2c_host_stress_all | 0 | 1 | 0.00 | ||
| V2 | host_maxperf | i2c_host_perf | 0 | 1 | 0.00 | ||
| V2 | host_override | i2c_host_override | 0 | 1 | 0.00 | ||
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 0 | 1 | 0.00 | ||
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 0 | 1 | 0.00 | ||
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0 | 1 | 0.00 | ||
| i2c_host_fifo_fmt_empty | 0 | 1 | 0.00 | ||||
| i2c_host_fifo_reset_rx | 0 | 1 | 0.00 | ||||
| V2 | host_fifo_full | i2c_host_fifo_full | 0 | 1 | 0.00 | ||
| V2 | host_timeout | i2c_host_stretch_timeout | 0 | 1 | 0.00 | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 0 | 1 | 0.00 | ||
| V2 | target_glitch | i2c_target_glitch | 0 | 1 | 0.00 | ||
| V2 | target_stress_all | i2c_target_stress_all | 0 | 1 | 0.00 | ||
| V2 | target_maxperf | i2c_target_perf | 0 | 1 | 0.00 | ||
| V2 | target_fifo_empty | i2c_target_stress_rd | 0 | 1 | 0.00 | ||
| i2c_target_intr_smoke | 0 | 1 | 0.00 | ||||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 0 | 1 | 0.00 | ||
| i2c_target_fifo_reset_tx | 0 | 1 | 0.00 | ||||
| V2 | target_fifo_full | i2c_target_stress_wr | 0 | 1 | 0.00 | ||
| i2c_target_stress_rd | 0 | 1 | 0.00 | ||||
| i2c_target_intr_stress_wr | 0 | 1 | 0.00 | ||||
| V2 | target_timeout | i2c_target_timeout | 0 | 1 | 0.00 | ||
| V2 | target_clock_stretch | i2c_target_stretch | 0 | 1 | 0.00 | ||
| V2 | bad_address | i2c_target_bad_addr | 0 | 1 | 0.00 | ||
| V2 | target_mode_glitch | i2c_target_hrst | 0 | 1 | 0.00 | ||
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 0 | 1 | 0.00 | ||
| i2c_target_fifo_watermarks_tx | 0 | 1 | 0.00 | ||||
| V2 | host_mode_config_perf | i2c_host_perf | 0 | 1 | 0.00 | ||
| i2c_host_perf_precise | 0 | 1 | 0.00 | ||||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 0 | 1 | 0.00 | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 0 | 1 | 0.00 | ||
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 0 | 1 | 0.00 | ||
| i2c_target_nack_acqfull_addr | 0 | 1 | 0.00 | ||||
| i2c_target_nack_txstretch | 0 | 1 | 0.00 | ||||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 0 | 1 | 0.00 | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 0 | 1 | 0.00 | ||
| V2 | alert_test | i2c_alert_test | 0 | 1 | 0.00 | ||
| V2 | intr_test | i2c_intr_test | 0.650s | 23.739us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.240s | 270.964us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.240s | 270.964us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 20.594s | 0 | 1 | 0.00 | |
| i2c_csr_rw | 24.777s | 0 | 1 | 0.00 | |||
| i2c_csr_aliasing | 1.050s | 137.428us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.900s | 168.911us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 20.594s | 0 | 1 | 0.00 | |
| i2c_csr_rw | 24.777s | 0 | 1 | 0.00 | |||
| i2c_csr_aliasing | 1.050s | 137.428us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 0.900s | 168.911us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 3 | 38 | 7.89 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.580s | 168.663us | 1 | 1 | 100.00 |
| i2c_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.580s | 168.663us | 1 | 1 | 100.00 |
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | target_error_intr | i2c_target_unexp_stop | 0 | 1 | 0.00 | ||
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 7 | 50 | 14.00 |
Job killed most likely because its dependent job failed. has 41 failures:
Test i2c_host_smoke has 1 failures.
Test i2c_host_override has 1 failures.
Test i2c_host_fifo_watermark has 1 failures.
Test i2c_host_fifo_overflow has 1 failures.
Test i2c_host_fifo_reset_fmt has 1 failures.
... and 36 more tests.
Job returned non-zero exit code has 3 failures:
Test default has 1 failures.
default
Log /nightly/current_run/scratch/master/i2c-sim-vcs/default/build.log
recompiling module tb
All of 83 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 17.246 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
Test i2c_csr_hw_reset has 1 failures.
0.i2c_csr_hw_reset.25493048525352537409932637980998083664863473212342130957049323910460893785204
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_csr_hw_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 16:27 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_csr_rw has 1 failures.
0.i2c_csr_rw.72970597652718407700604968875068529952782923165727069210549081306014337844919
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 23 16:28 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255