KMAC/MASKED Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 43.290s 3.725ms 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 0 1 0.00
V1 csr_rw kmac_csr_rw 0 1 0.00
V1 csr_bit_bash kmac_csr_bit_bash 0 1 0.00
V1 csr_aliasing kmac_csr_aliasing 0 1 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 0 1 0.00
kmac_csr_aliasing 0 1 0.00
V1 mem_walk kmac_mem_walk 0 1 0.00
V1 mem_partial_access kmac_mem_partial_access 0 1 0.00
V1 TOTAL 1 8 12.50
V2 long_msg_and_output kmac_long_msg_and_output 34.968m 312.127ms 1 1 100.00
V2 burst_write kmac_burst_write 12.336m 11.169ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 25.156m 63.806ms 1 1 100.00
kmac_test_vectors_sha3_256 19.873m 130.883ms 1 1 100.00
kmac_test_vectors_sha3_384 18.958m 45.155ms 1 1 100.00
kmac_test_vectors_sha3_512 12.309m 67.670ms 1 1 100.00
kmac_test_vectors_shake_128 30.105m 795.043ms 1 1 100.00
kmac_test_vectors_shake_256 19.819m 16.737ms 1 1 100.00
kmac_test_vectors_kmac 2.310s 410.239us 1 1 100.00
kmac_test_vectors_kmac_xof 2.120s 158.984us 1 1 100.00
V2 sideload kmac_sideload 4.431m 5.480ms 1 1 100.00
V2 app kmac_app 1.869m 13.115ms 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 48.330s 1.977ms 1 1 100.00
V2 entropy_refresh kmac_entropy_refresh 3.906m 40.730ms 1 1 100.00
V2 error kmac_error 31.870s 702.077us 1 1 100.00
V2 key_error kmac_key_error 2.630s 1.486ms 1 1 100.00
V2 sideload_invalid kmac_sideload_invalid 2.590s 126.759us 1 1 100.00
V2 edn_timeout_error kmac_edn_timeout_error 0.980s 34.526us 1 1 100.00
V2 entropy_mode_error kmac_entropy_mode_error 0.850s 108.626us 1 1 100.00
V2 entropy_ready_error kmac_entropy_ready_error 26.465s 0 1 0.00
V2 lc_escalation kmac_lc_escalation 1.200s 92.597us 1 1 100.00
V2 stress_all kmac_stress_all 23.616m 221.584ms 1 1 100.00
V2 intr_test kmac_intr_test 0 1 0.00
V2 alert_test kmac_alert_test 0.720s 47.557us 1 1 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 0 1 0.00
V2 tl_d_illegal_access kmac_tl_errors 0 1 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0 1 0.00
kmac_csr_rw 0 1 0.00
kmac_csr_aliasing 0 1 0.00
kmac_same_csr_outstanding 0 1 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 0 1 0.00
kmac_csr_rw 0 1 0.00
kmac_csr_aliasing 0 1 0.00
kmac_same_csr_outstanding 0 1 0.00
V2 TOTAL 22 26 84.62
V2S shadow_reg_update_error kmac_shadow_reg_errors 0 1 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 0 1 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 0 1 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 0 1 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 0 1 0.00
V2S tl_intg_err kmac_sec_cm 19.323s 0 1 0.00
kmac_tl_intg_err 0 1 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 0 1 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 1.200s 92.597us 1 1 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 43.290s 3.725ms 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 4.431m 5.480ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 0 1 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 19.323s 0 1 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 19.323s 0 1 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 19.323s 0 1 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 43.290s 3.725ms 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 1.200s 92.597us 1 1 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 19.323s 0 1 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 1.896m 3.707ms 1 1 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 43.290s 3.725ms 1 1 100.00
V2S TOTAL 1 5 20.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.525m 5.644ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 25 40 62.50

Failure Buckets