KMAC/UNMASKED Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.930s	570.792us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.880s	18.063us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.820s	21.347us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.470s	1.943ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	2.920s	75.224us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.710s	70.872us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.820s	21.347us	1	1	100.00
		kmac_csr_aliasing	2.920s	75.224us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.700s	13.785us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.000s	34.067us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.332m	63.562ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.277m	3.493ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	16.360m	70.772ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.820s	2.472ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.704m	907.561ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.610s	1.112ms	1	1	100.00
		kmac_test_vectors_shake_128	2.262m	50.477ms	1	1	100.00
		kmac_test_vectors_shake_256	24.986m	188.089ms	1	1	100.00
		kmac_test_vectors_kmac	1.400s	74.200us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.450s	82.284us	1	1	100.00
V2	sideload	kmac_sideload	4.373m	243.273ms	1	1	100.00
V2	app	kmac_app	1.151m	9.311ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.289m	99.179ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.694m	7.859ms	1	1	100.00
V2	error	kmac_error	3.885m	26.257ms	1	1	100.00
V2	key_error	kmac_key_error	4.380s	4.810ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	15.684s		0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.860s	3.199ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	20.200s	3.425ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	24.710s	7.569ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.090s	48.948us	1	1	100.00
V2	stress_all	kmac_stress_all	6.832m	7.471ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.750s	32.393us	1	1	100.00
V2	alert_test	kmac_alert_test	0.710s	26.000us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.020s	468.510us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.020s	468.510us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.880s	18.063us	1	1	100.00
		kmac_csr_rw	0.820s	21.347us	1	1	100.00
		kmac_csr_aliasing	2.920s	75.224us	1	1	100.00
		kmac_same_csr_outstanding	1.760s	565.127us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.880s	18.063us	1	1	100.00
		kmac_csr_rw	0.820s	21.347us	1	1	100.00
		kmac_csr_aliasing	2.920s	75.224us	1	1	100.00
		kmac_same_csr_outstanding	1.760s	565.127us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.050s	31.271us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.050s	31.271us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.050s	31.271us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.050s	31.271us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.720s	916.936us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	18.490s	5.953ms	1	1	100.00
		kmac_tl_intg_err	3.040s	409.290us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.040s	409.290us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.090s	48.948us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.930s	570.792us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.373m	243.273ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.050s	31.271us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	18.490s	5.953ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	18.490s	5.953ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	18.490s	5.953ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.930s	570.792us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.090s	48.948us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	18.490s	5.953ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.754m	11.200ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.930s	570.792us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.810s	3.764ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.102841947076140166653110222507350894581097163473624179930075957095170649613363
      Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:13 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255