PRIM_LFSR Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	Unmapped tests	prim_lfsr_gal_test	2.448m	336.384ms	1	1	100.00
		prim_lfsr_gal_smoke			0	1	0.00
		prim_lfsr_fib_test	2.465m	336.994ms	1	1	100.00
		prim_lfsr_fib_smoke			0	1	0.00
		TOTAL			2	4	50.00

Failure Buckets

• Job killed most likely because its dependent job failed. has 2 failures:

  • Test prim_lfsr_gal_smoke has 1 failures.

    • 0.prim_lfsr_gal_smoke.89535562387604372991282152909780447583344531977744926251866844218523485752101
      Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest/run.log

  • Test prim_lfsr_fib_smoke has 1 failures.

    • 0.prim_lfsr_fib_smoke.21689176544254668316505173120703229453057912373237319915616211177061455474861
      Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest/run.log

• Job returned non-zero exit code has 1 failures:

  • Test prim_lfsr_dw_8_gal has 1 failures.

    • prim_lfsr_dw_8_gal
      Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/build.log

        recompiling module prim_lfsr_tb
        All of 16 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 6.400 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
      

• Job timed out after * minutes has 1 failures:

  • Test prim_lfsr_dw_8_fib has 1 failures.

    • prim_lfsr_dw_8_fib
      Log /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/build.log

        Job timed out after 60 minutes