ROM_CTRL/32KB Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.580s 180.610us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.140s 304.803us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 2.760s 388.132us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.960s 164.623us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.950s 168.424us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.090s 143.955us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 2.760s 388.132us 1 1 100.00
rom_ctrl_csr_aliasing 3.950s 168.424us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.250s 1.171ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.290s 539.027us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 3.480s 308.174us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.180s 2.343ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.950s 411.326us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.640s 299.366us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 4.010s 1.078ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 4.010s 1.078ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.140s 304.803us 1 1 100.00
rom_ctrl_csr_rw 2.760s 388.132us 1 1 100.00
rom_ctrl_csr_aliasing 3.950s 168.424us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.300s 127.004us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.140s 304.803us 1 1 100.00
rom_ctrl_csr_rw 2.760s 388.132us 1 1 100.00
rom_ctrl_csr_aliasing 3.950s 168.424us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.300s 127.004us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.930s 573.634us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.002m 3.911ms 1 1 100.00
rom_ctrl_tl_intg_err 39.930s 518.915us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.002m 3.911ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.002m 3.911ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.002m 3.911ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.002m 3.911ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.580s 180.610us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.580s 180.610us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.580s 180.610us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 39.930s 518.915us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.950s 411.326us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 52.040s 3.727ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.930s 573.634us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.002m 3.911ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.674m 14.692ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00