ROM_CTRL/64KB Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.380s	1.264ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.710s	261.210us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.170s	1.486ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.650s	376.337us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.830s	208.922us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.170s	1.486ms	1	1	100.00
		rom_ctrl_csr_aliasing	5.830s	208.922us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.287s		0	1	0.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.930s	292.758us	1	1	100.00
V1		TOTAL			6	8	75.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.270s	822.336us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	22.970s	821.232us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	18.331s		0	1	0.00
V2	alert_test	rom_ctrl_alert_test	6.420s	1.934ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.300s	1.810ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.300s	1.810ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.710s	261.210us	1	1	100.00
		rom_ctrl_csr_rw	6.170s	1.486ms	1	1	100.00
		rom_ctrl_csr_aliasing	5.830s	208.922us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.870s	216.930us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.710s	261.210us	1	1	100.00
		rom_ctrl_csr_rw	6.170s	1.486ms	1	1	100.00
		rom_ctrl_csr_aliasing	5.830s	208.922us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.870s	216.930us	1	1	100.00
V2		TOTAL			5	6	83.33
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	38.580s	1.630ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.676m	822.717us	0	1	0.00
		rom_ctrl_tl_intg_err	1.526m	440.812us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.676m	822.717us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.676m	822.717us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.676m	822.717us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.676m	822.717us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.380s	1.264ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.380s	1.264ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.380s	1.264ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.526m	440.812us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
		rom_ctrl_kmac_err_chk	18.331s		0	1	0.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.812m	98.855ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	38.580s	1.630ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.676m	822.717us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.687m	11.415ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			15	19	78.95

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 0.rom_ctrl_kmac_err_chk.77853070629513976740449212886851671430094121610356630334720070839686403344525
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:22 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test rom_ctrl_mem_walk has 1 failures.

    • 0.rom_ctrl_mem_walk.43387245778251213069713714630918624038047544007933670553856981272222860051648
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_mem_walk/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:27 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.106359128756444212915629064366366951300916496439341948742023966296807215823048
      Line 114, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 24548762ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 24548762ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 24548762ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

• Job timed out after * minutes has 1 failures:

  • Test rom_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rom_ctrl_csr_mem_rw_with_rand_reset.59195659693057211838337133126925467915019526322180040587707015527810744475366
      Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        Job timed out after 60 minutes