RV_DM/USE_DMI_INTERFACE Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 0 1 0.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0 1 0.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0 1 0.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 0 1 0.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0 1 0.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 0 1 0.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 0 1 0.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 0 1 0.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 0 1 0.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 0 1 0.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0 1 0.00
V1 cmderr_exception rv_dm_cmderr_exception 0 1 0.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0 1 0.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0 1 0.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0 1 0.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0 1 0.00
V1 halt_resume rv_dm_halt_resume_whereto 0 1 0.00
V1 progbuf_busy rv_dm_cmderr_busy 0 1 0.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0 1 0.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0 1 0.00
V1 progbuf_exception rv_dm_cmderr_exception 0 1 0.00
V1 rom_read_access rv_dm_rom_read_access 0 1 0.00
V1 csr_hw_reset rv_dm_csr_hw_reset 0 1 0.00
V1 csr_rw rv_dm_csr_rw 0 1 0.00
V1 csr_bit_bash rv_dm_csr_bit_bash 0 1 0.00
V1 csr_aliasing rv_dm_csr_aliasing 0 1 0.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 0 1 0.00
rv_dm_csr_rw 0 1 0.00
V1 mem_walk rv_dm_mem_walk 0 1 0.00
V1 mem_partial_access rv_dm_mem_partial_access 0 1 0.00
V1 TOTAL 0 27 0.00
V2 idcode rv_dm_smoke 0 1 0.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 0 1 0.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0 1 0.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0 1 0.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0 1 0.00
V2 sba rv_dm_sba_tl_access 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 0 1 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0 1 0.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 0 1 0.00
V2 ndmreset_req rv_dm_ndmreset_req 0 1 0.00
V2 hart_unavail rv_dm_hart_unavail 0 1 0.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 0 1 0.00
rv_dm_tap_fsm_rand_reset 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 0 1 0.00
V2 stress_all rv_dm_stress_all 0 1 0.00
V2 alert_test rv_dm_alert_test 0 1 0.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 0 1 0.00
rv_dm_csr_hw_reset 0 1 0.00
rv_dm_csr_rw 0 1 0.00
rv_dm_same_csr_outstanding 0 1 0.00
V2 tl_d_partial_access rv_dm_csr_aliasing 0 1 0.00
rv_dm_csr_hw_reset 0 1 0.00
rv_dm_csr_rw 0 1 0.00
rv_dm_same_csr_outstanding 0 1 0.00
V2 TOTAL 0 19 0.00
V2S tl_intg_err rv_dm_sec_cm 0 1 0.00
rv_dm_tl_intg_err 0 1 0.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 0 1 0.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 0 1 0.00
rv_dm_debug_disabled 0 1 0.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 0 1 0.00
rv_dm_debug_disabled 0 1 0.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 0 1 0.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 0 1 0.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0 1 0.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0 1 0.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 0 1 0.00
V2S TOTAL 0 5 0.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 0 1 0.00
TOTAL 0 53 0.00

Failure Buckets