RV_TIMER Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.020s	1.395ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.510s	25.117us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.560s	21.645us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.580s	1.413ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.580s	26.875us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.580s	37.293us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.560s	21.645us	1	1	100.00
		rv_timer_csr_aliasing	0.580s	26.875us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.590s	195.996us	0	1	0.00
V2	disabled	rv_timer_disabled	2.990s	2.686ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	0.850s	1.112ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	0.850s	1.112ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.770s	8.892ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.520s	37.382us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.500s	36.231us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.660s	152.348us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.660s	152.348us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.510s	25.117us	1	1	100.00
		rv_timer_csr_rw	0.560s	21.645us	1	1	100.00
		rv_timer_csr_aliasing	0.580s	26.875us	1	1	100.00
		rv_timer_same_csr_outstanding	0.570s	21.015us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.510s	25.117us	1	1	100.00
		rv_timer_csr_rw	0.560s	21.645us	1	1	100.00
		rv_timer_csr_aliasing	0.580s	26.875us	1	1	100.00
		rv_timer_same_csr_outstanding	0.570s	21.015us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.700s	34.368us	1	1	100.00
		rv_timer_tl_intg_err	24.365s		0	1	0.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	24.365s		0	1	0.00
V2S		TOTAL			1	2	50.00
V3	min_value	rv_timer_min	0.520s	18.150us	1	1	100.00
V3	max_value	rv_timer_max	0.560s	45.915us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.510s	3.385ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			16	19	84.21

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.85270517940891661819594130554758145946676253874471571397855153341594323568553
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  45914777 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  45914777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.93402313967334015832917439655548761205865136574118431362314526572925972355172
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 195996055 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf3126b04) == 0x1
        UVM_INFO @ 195996055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test rv_timer_tl_intg_err has 1 failures.

    • 0.rv_timer_tl_intg_err.31841280813549102218309074581116212615934275914816572574918662192258393695048
      Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:18 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255