SPI_DEVICE/1R1W Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.030s	1.969ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.930s	34.536us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.770s	526.860us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	7.840s	861.215us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.110s	1.142ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.030s	425.244us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.770s	526.860us	1	1	100.00
		spi_device_csr_aliasing	5.110s	1.142ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	33.619us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.070s	138.960us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.750s	32.423us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.630s	6.369us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	6.047us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.530s	331.570us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.530s	331.570us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.140s	7.335ms	1	1	100.00
		spi_device_tpm_sts_read	0.640s	20.700us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.050s	2.264ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	14.680s	27.078ms	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.380s	244.971us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.380s	244.971us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.140s	538.689us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.140s	538.689us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.140s	538.689us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.140s	538.689us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.140s	538.689us	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.570s	476.748us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.390s	15.436ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.390s	15.436ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.390s	15.436ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.900s	142.853us	1	1	100.00
		spi_device_read_buffer_direct	4.080s	310.046us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.390s	15.436ms	1	1	100.00
		spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	45.580s	12.339ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.710s	119.075us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.710s	119.075us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.030s	1.969ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.678m	73.458ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.045m	23.634ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.660s	41.845us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.680s	227.701us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.740s	147.353us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.740s	147.353us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.930s	34.536us	1	1	100.00
		spi_device_csr_rw	1.770s	526.860us	1	1	100.00
		spi_device_csr_aliasing	5.110s	1.142ms	1	1	100.00
		spi_device_same_csr_outstanding	1.260s	43.489us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.930s	34.536us	1	1	100.00
		spi_device_csr_rw	1.770s	526.860us	1	1	100.00
		spi_device_csr_aliasing	5.110s	1.142ms	1	1	100.00
		spi_device_same_csr_outstanding	1.260s	43.489us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	20.018s		0	1	0.00
		spi_device_tl_intg_err	16.000s	4.174ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.000s	4.174ms	1	1	100.00
V2S		TOTAL			1	2	50.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.038m	29.986ms	1	1	100.00
		TOTAL			30	33	90.91

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.81685416638956948921456556304402742056833604620013261935813571452932241675544
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4827740 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[74])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4827740 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4827740 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[970])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.99002772721398204812484267433312816141556755708141474153458249378112449757089
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3377874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfcb46b [111111001011010001101011] vs 0x0 [0])
        UVM_ERROR @   3462874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa261c1 [101000100110000111000001] vs 0x0 [0])
        UVM_ERROR @   3522874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdcedbb [110111001110110110111011] vs 0x0 [0])
        UVM_ERROR @   3528874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x48b4ac [10010001011010010101100] vs 0x0 [0])
        UVM_ERROR @   3563874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x14adf0 [101001010110111110000] vs 0x0 [0])
      

• Job returned non-zero exit code has 1 failures:

  • Test spi_device_sec_cm has 1 failures.

    • 0.spi_device_sec_cm.68597776823840697234831875064021423547360669529389764090488888060416911648709
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest/run.log

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