SRAM_CTRL/MAIN Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.030s	3.403ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.610s	69.123us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.620s	18.276us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.410s	66.880us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.670s	54.280us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.630s	1.361ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.620s	18.276us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	54.280us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.958m	82.675ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.806m	16.363ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.076m	27.005ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.206m	11.549ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.164m	18.893ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.379m	20.023ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	35.320s	66.692ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.199m	50.785ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.820s	3.704ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.231m	29.991ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	37.660s	12.709ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.180s	3.370ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.050s	2.518ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	17.600s	1.713ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.110s	1.105ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	19.276m	57.695ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	24.326us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.810s	708.192us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.810s	708.192us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.610s	69.123us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	18.276us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	54.280us	1	1	100.00
		sram_ctrl_same_csr_outstanding	15.584s		0	1	0.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.610s	69.123us	1	1	100.00
		sram_ctrl_csr_rw	0.620s	18.276us	1	1	100.00
		sram_ctrl_csr_aliasing	0.670s	54.280us	1	1	100.00
		sram_ctrl_same_csr_outstanding	15.584s		0	1	0.00
V2		TOTAL			16	17	94.12
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.050s	7.392ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.590s	3.921us	0	1	0.00
		sram_ctrl_tl_intg_err	1.250s	99.581us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.590s	3.921us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.250s	99.581us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	17.600s	1.713ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	17.600s	1.713ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.620s	18.276us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.199m	50.785ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.199m	50.785ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.199m	50.785ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	35.320s	66.692ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.580s	1.214ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.050s	7.392ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.490s	2.640ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.030s	3.403ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.030s	3.403ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.199m	50.785ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.590s	3.921us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	35.320s	66.692ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.590s	3.921us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.590s	3.921us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.030s	3.403ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.590s	3.921us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.950s	1.116ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.80704975429908383291182648808201685989313906176704583954759259267207890383950
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3921196 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3921196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test sram_ctrl_same_csr_outstanding has 1 failures.

    • 0.sram_ctrl_same_csr_outstanding.6222515935181577031411850865041190952307993321280621007438021332611973937649
      Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest/run.log

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        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255