SRAM_CTRL/RET Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	31.240s	563.753us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.610s	25.071us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.630s	16.646us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.530s	501.511us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.650s	12.414us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.790s	46.817us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.630s	16.646us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	12.414us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.100s	306.749us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.240s	279.549us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	59.300s	13.944ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.583m	4.157ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.760s	2.929ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.150m	6.262ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.360s	1.919ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.620m	5.864ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	31.730s	1.319ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.659m	15.889ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	16.296s		0	1	0.00
		sram_ctrl_throughput_w_partial_write	16.060s	404.295us	1	1	100.00
		sram_ctrl_throughput_w_readback	31.620s	1.020ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.768m	10.432ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.670s	26.729us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	2.564m	9.752ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.650s	14.708us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.560s	130.251us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.560s	130.251us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.610s	25.071us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	16.646us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	12.414us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	96.019us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.610s	25.071us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	16.646us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	12.414us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.680s	96.019us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.110s	399.011us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.600s	4.910us	0	1	0.00
		sram_ctrl_tl_intg_err	1.210s	346.580us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.600s	4.910us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.210s	346.580us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.768m	10.432ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.768m	10.432ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.630s	16.646us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.620m	5.864ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.620m	5.864ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.620m	5.864ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.360s	1.919ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.870s	46.807us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.110s	399.011us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.870s	125.221us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	31.240s	563.753us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	31.240s	563.753us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.620m	5.864ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.600s	4.910us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.360s	1.919ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.600s	4.910us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.600s	4.910us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	31.240s	563.753us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.600s	4.910us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	47.610s	2.953ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test sram_ctrl_max_throughput has 1 failures.

    • 0.sram_ctrl_max_throughput.87170740784584021903541317683561818690722347803920754837587456963229053955587
      Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:13 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.19753488114830031203684397334907649808019709385922123382119693694817641524795
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4909901 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4909901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---