UART Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: 4330c70

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	4.890s	6.075ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	15.226us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.570s	28.895us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.170s	94.311us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.730s	171.961us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.610s	66.409us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.570s	28.895us	1	1	100.00
		uart_csr_aliasing	0.730s	171.961us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	18.890s	38.346ms	1	1	100.00
V2	parity	uart_smoke	4.890s	6.075ms	1	1	100.00
		uart_tx_rx	18.890s	38.346ms	1	1	100.00
V2	parity_error	uart_intr	2.332m	147.408ms	1	1	100.00
		uart_rx_parity_err	53.680s	206.713ms	1	1	100.00
V2	watermark	uart_tx_rx	18.890s	38.346ms	1	1	100.00
		uart_intr	2.332m	147.408ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.313m	122.373ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	3.880s	41.945ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	30.570s	22.193ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.332m	147.408ms	1	1	100.00
V2	rx_break_err	uart_intr	2.332m	147.408ms	1	1	100.00
V2	rx_timeout	uart_intr	2.332m	147.408ms	1	1	100.00
V2	perf	uart_perf	22.105s		0	1	0.00
V2	sys_loopback	uart_loopback	1.940s	4.396ms	1	1	100.00
V2	line_loopback	uart_loopback	1.940s	4.396ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	13.000s	25.313ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.120s	6.542ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.710s	2.633ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.280s	1.899ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.856m	173.548ms	1	1	100.00
V2	stress_all	uart_stress_all	46.420s	163.661ms	0	1	0.00
V2	alert_test	uart_alert_test	0.530s	13.216us	1	1	100.00
V2	intr_test	uart_intr_test	0.540s	12.349us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.540s	499.512us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.540s	499.512us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	15.226us	1	1	100.00
		uart_csr_rw	0.570s	28.895us	1	1	100.00
		uart_csr_aliasing	0.730s	171.961us	1	1	100.00
		uart_same_csr_outstanding	0.710s	231.963us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	15.226us	1	1	100.00
		uart_csr_rw	0.570s	28.895us	1	1	100.00
		uart_csr_aliasing	0.730s	171.961us	1	1	100.00
		uart_same_csr_outstanding	0.710s	231.963us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.670s	138.321us	1	1	100.00
		uart_tl_intg_err	45.867s		0	1	0.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	45.867s		0	1	0.00
V2S		TOTAL			1	2	50.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.720s	3.848ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	27	88.89

Failure Buckets

• Job returned non-zero exit code has 2 failures:

  • Test uart_perf has 1 failures.

    • 0.uart_perf.19206398816608705694682867057845735940562305561201573982602904912787653707055
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_perf/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

  • Test uart_tl_intg_err has 1 failures.

    • 0.uart_tl_intg_err.83234548641406261648588046310876263203176746522928214372263740136556369483130
      Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_tl_intg_err/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 23 16:19 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
      

• UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.60102346900041463788440704978925517342306834584967267810248849679530770638899
      Line 88, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 161211376510 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
        UVM_ERROR @ 161211376510 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
        UVM_ERROR @ 161211376510 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
        UVM_ERROR @ 161300922860 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 161300968315 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty