CHIP Simulation Results

Tuesday September 23 2025 16:10:41 UTC

GitHub Revision: `4330c70`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	10.915s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	10.915s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	13.857s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.499s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.814s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	14.788s		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	14.788s		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	14.788s		0	1	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	14.662s		0	1	0.00
		chip_sw_example_manufacturer	14.158s		0	1	0.00
		chip_sw_example_concurrency	10.393s		0	1	0.00
		chip_sw_uart_smoketest_signed	1.030m		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.080s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.160s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.160s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.510s	12.968us	1	1	100.00
V1		TOTAL			1	12	8.33
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	10.757s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.671s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	14.350s		0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	10.353s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	15.098s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	10.457s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.417s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes			0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes			0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.673s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	10.913s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.516s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.516s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.654m	4.718ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	43.157s		0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	26.570s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.228s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	26.770s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.046m	17.593ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	14.183s		0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	14.391s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	14.391s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.160s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.209s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.209s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	14.264s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	16.011s		0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	14.235s		0	1	0.00
		chip_sw_aes_idle	14.728s		0	1	0.00
		chip_sw_hmac_enc_idle	14.518s		0	1	0.00
		chip_sw_kmac_idle	15.798s		0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	15.273s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	15.780s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	10.337s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.641s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.261s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.587s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.152s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.101s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.869s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.753s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.303s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.261s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.587s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.152s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.101s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.869s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.753s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.303s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.841s		0	1	0.00
		chip_sw_aes_enc_jitter_en	14.553s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.345s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.225s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	15.740s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.079s		0	1	0.00
		chip_sw_clkmgr_jitter	14.419s		0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	26.374s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	27.246s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	27.565s		0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	26.365s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	26.903s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	26.685s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	15.974s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	10.360s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	14.023s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.965s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	14.419s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	10.442s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.653s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	14.209s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.298s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.653s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.301s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.360s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.300s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.475s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	14.126s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	10.442s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	26.570s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.356s		0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	13.416s		0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.357s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	10.349s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	10.442s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.070s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.772s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	10.442s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.859s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.357s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.534s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.642s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.866s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.806s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.685s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.531s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.772s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.411s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	14.633s		0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.560s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.414s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.529s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.848s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	14.226s		0	1	0.00
		chip_sw_rom_ctrl_integrity_check	15.850s		0	1	0.00
		chip_sw_sram_ctrl_execution_main	15.853s		0	1	0.00
		chip_prim_tl_access	9.962m	16.439ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.261s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.587s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.152s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	15.101s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.869s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.753s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.303s		0	1	0.00
		chip_rv_dm_lc_disabled	8.046m	17.593ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	15.022s		0	1	0.00
		chip_sw_aes_enc_jitter_en	14.553s		0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	14.531s		0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	14.728s		0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	14.754s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.345s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	14.518s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	12.774s		0	1	0.00
		chip_sw_kmac_mode_kmac	15.739s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	15.740s		0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	14.226s		0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	16.245s		0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.305s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	15.798s		0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.043s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.043s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.802s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	14.863s		0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.987s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	14.226s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.225s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.100s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.841s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	14.235s		0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	14.235s		0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	14.235s		0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	13.705s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	15.850s		0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	15.850s		0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	15.851s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.079s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.853s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	10.442s		0	1	0.00
		chip_sw_data_integrity_escalation	15.516s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	13.705s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	14.226s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	15.851s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	27.681s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	13.705s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	14.226s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	15.851s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	27.681s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.795s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.411s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.560s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.414s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.529s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	14.848s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.841s		0	1	0.00
		chip_prim_tl_access	9.962m	16.439ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.962m	16.439ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.630s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.841s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	14.023s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.841s		0	1	0.00
		chip_sw_aes_enc_jitter_en	14.553s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	14.345s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.225s		0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	15.740s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.079s		0	1	0.00
		chip_sw_clkmgr_jitter	14.419s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.345s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.345s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	10.446s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	14.313s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	14.526s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	12.513s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	13.432s		0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	27.470s		0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	27.681s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	14.356s		0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	14.356s		0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	1.022m		0	1	0.00
		chip_sw_aon_timer_smoketest	1.022m		0	1	0.00
		chip_sw_clkmgr_smoketest	1.016m		0	1	0.00
		chip_sw_csrng_smoketest	1.007m		0	1	0.00
		chip_sw_gpio_smoketest	1.006m		0	1	0.00
		chip_sw_hmac_smoketest	59.880s		0	1	0.00
		chip_sw_kmac_smoketest	59.359s		0	1	0.00
		chip_sw_otbn_smoketest	59.351s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	59.030s		0	1	0.00
		chip_sw_rv_plic_smoketest	59.339s		0	1	0.00
		chip_sw_rv_timer_smoketest	59.437s		0	1	0.00
		chip_sw_rstmgr_smoketest	10.224s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	14.417s		0	1	0.00
		chip_sw_uart_smoketest	14.465s		0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	1.031m		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	1.030m		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	10.757s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	20.455s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	13.985s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	10.272s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	15.738s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	20.331s		0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.279s		0	1	0.00
		chip_rv_dm_lc_disabled	8.046m	17.593ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	20.346s		0	1	0.00
		chip_sw_lc_walkthrough_prod	20.245s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	19.847s		0	1	0.00
		chip_sw_lc_walkthrough_rma	19.363s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	19.279s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	19.801s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	19.411s		0	1	0.00
		rom_volatile_raw_unlock	10.327s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.542s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	14.385s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	14.574s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	28.631s		0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	28.631s		0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.160s		0	1	0.00
		chip_same_csr_outstanding	7.920s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.160s		0	1	0.00
		chip_same_csr_outstanding	7.920s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.370m	227.967us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.500s	12.302us	1	1	100.00
		xbar_smoke_large_delays	4.413m	2.565ms	1	1	100.00
		xbar_smoke_slow_rsp	4.882m	2.001ms	1	1	100.00
		xbar_random_zero_delays	1.276m	78.097us	1	1	100.00
		xbar_random_large_delays	8.555m	5.087ms	1	1	100.00
		xbar_random_slow_rsp	27.927m	11.753ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	41.740s	30.725us	1	1	100.00
		xbar_error_and_unmapped_addr	13.860s	15.520us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.428m	303.202us	1	1	100.00
		xbar_error_and_unmapped_addr	13.860s	15.520us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	33.003s		0	1	0.00
		xbar_access_same_device_slow_rsp	10.196m	4.246ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	38.525s		0	1	0.00
V2	xbar_stress_all	xbar_stress_all	7.413m	426.408us	1	1	100.00
		xbar_stress_all_with_error	2.498m	155.000us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	39.913m	5.945ms	1	1	100.00
		xbar_stress_all_with_reset_error	26.248s		0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	19.966s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	19.637s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	20.568s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	19.966s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	19.036s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	19.914s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	19.473s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	18.984s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	19.479s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.533s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	14.646s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.699s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.442s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	14.668s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	14.717s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	15.671s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.923s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.937s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.669s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	14.920s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.023s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	14.645s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.110s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.707s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.490s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.953s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.936s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	10.570s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	10.678s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.274s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.610s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.002s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.001s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	15.019s		0	1	0.00
		rom_e2e_asm_init_dev	14.801s		0	1	0.00
		rom_e2e_asm_init_prod	14.583s		0	1	0.00
		rom_e2e_asm_init_prod_end	14.981s		0	1	0.00
		rom_e2e_asm_init_rma	14.879s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.343s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.394s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.546s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.551s		0	1	0.00
V2		TOTAL			16	205	7.80
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	14.546s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	27.630s		0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	14.494s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.147s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.508s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	27.199s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	10.442s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	14.419s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.850s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	15.735s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.560s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	14.494s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.147s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.508s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	13.849s		0	1	0.00
		rom_e2e_jtag_inject_dev	14.610s		0	1	0.00
		rom_e2e_jtag_inject_rma	13.803s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.080m		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	16.243s		0	1	0.00
		chip_sw_entropy_src_kat_test	14.352s		0	1	0.00
		chip_sw_entropy_src_ast_rng_req	14.349s		0	1	0.00
		chip_plic_all_irqs_0	16.071s		0	1	0.00
		chip_plic_all_irqs_10	16.177s		0	1	0.00
		chip_sw_dma_inline_hashing	20.505s		0	1	0.00
		chip_sw_dma_abort	19.796s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.705s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.589s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.545s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.596s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.545s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.593s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.693s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.915s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.535s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.543s		0	1	0.00
		chip_sw_entropy_src_smoketest	1.009m		0	1	0.00
		chip_sw_mbx_smoketest	1.005m		0	1	0.00
		TOTAL			17	250	6.80

Failure Buckets

Job returned non-zero exit code has 228 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.1318031633454961948259520293039859770784353867455745803288389950036905764078
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
  Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_rom_sim_dv
  Computing main repo mapping:
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.74429629903231836743007661439513791258797896042653424154881056220161680046180
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "@manufacturer_test_hooks//:example_test_sim_dv".
  Building "@manufacturer_test_hooks//:example_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true @manufacturer_test_hooks//:example_test_sim_dv
  Another command (pid=887318) is running. Waiting for it to complete on the server (server_pid=882514)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.81555128414328329143159802199612894599841150705580631254971338284747345246123
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_concurrency_test_sim_dv".
  Building "//sw/device/tests:example_concurrency_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_concurrency_test_sim_dv
  Another command (pid=887318) is running. Waiting for it to complete on the server (server_pid=882514)...
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_all_escalation_resets has 1 failures.

0.chip_sw_all_escalation_resets.83780808694444147556664269818791777556159049986218655923385564307573369315494
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv".
  Building "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv
  Computing main repo mapping:
  ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel: Unknown host: bcr.bazel.build
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.95566673988647841226035965113022134236464689279286285534410388945030615739869
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

    <builtin>: in <toplevel>
  Repository rule http_archive defined at:
    /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:392:31: in <toplevel>
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl:137:45: An error occurred during the fetch of repository 'lowrisc_misc_linters+':
     Traceback (most recent call last):
      File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/build_defs/repo/http.bzl", line 137, column 45, in _http_archive_impl
          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp6265864227716886465/20250217_01.tar.gz: Unknown host: codeload.github.com
  ERROR: Error computing the main repository mapping: error during computation of main repo mapping: java.io.IOException: Error downloading [https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/lowrisc_misc_linters+/temp6265864227716886465/20250217_01.tar.gz: Unknown host: codeload.github.com
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

... and 223 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.93962938288054833960272646499490853556142463135541793076915872704772826331388
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.87350301213906052621425586712179850276187129164033277346129805882589677823148
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.88656216457166950008347429076155809270578771734290383417458506044084263284237
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test pad_ctrl_test_mode has 1 failures.
  - pad_ctrl_test_mode
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/build.log
```
  Job timed out after 60 minutes
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.110338057451116875770786572649873432580218898069579678968422968153184645414465
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4718.332927 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h23bd58b2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2c  a_opcode: 'h0  a_user: 'h2697a  d_param: 'h0  d_source: 'h2c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4718.332927 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job killed most likely because its dependent job failed. has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.64800253203091768119293077387810232182396069434099531358335482738363466684012
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log