DMA Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	1.158ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	238.813us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	348.383us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	103.077us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	27.296us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	5.000s	159.573us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	3.000s	210.885us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	154.845us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	27.296us	1	1	100.00
		dma_csr_aliasing	3.000s	210.885us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.350m	26.895ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	4.967m	113.138ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	8.017m	42.277ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.017m	42.277ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.967m	113.138ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.317m	29.238ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.017m	42.277ms	1	1	100.00
V2	dma_abort	dma_abort	5.000s	485.947us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.633m	8.718ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	36.085us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	11.903us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	359.983us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	359.983us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	103.077us	1	1	100.00
		dma_csr_rw	2.000s	27.296us	1	1	100.00
		dma_csr_aliasing	3.000s	210.885us	1	1	100.00
		dma_same_csr_outstanding	2.000s	51.956us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	103.077us	1	1	100.00
		dma_csr_rw	2.000s	27.296us	1	1	100.00
		dma_csr_aliasing	3.000s	210.885us	1	1	100.00
		dma_same_csr_outstanding	2.000s	51.956us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	24.000s	1.597ms	1	1	100.00
		dma_generic_stress	5.317m	29.238ms	1	1	100.00
		dma_handshake_stress	8.017m	42.277ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	1.905ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	405.255us	1	1	100.00
		dma_sec_cm	1.000s	10.179us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.817m	105.519ms	1	1	100.00
		dma_longer_transfer	5.000s	445.527us	1	1	100.00
		dma_stress_all_with_rand_reset	4.000s	124.665us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.90427012391164151588738079526279482419986982340405360110375877933703489570632
      Line 89, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  124664643ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  124664643ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---