EDN Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.850s	17.926us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.850s	51.463us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.870s	31.893us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.400s	336.752us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.470s	62.464us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.850s	53.178us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.870s	31.893us	1	1	100.00
		edn_csr_aliasing	1.470s	62.464us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.040s	39.088us	1	1	100.00
V2	csrng_commands	edn_genbits	1.040s	39.088us	1	1	100.00
V2	genbits	edn_genbits	1.040s	39.088us	1	1	100.00
V2	interrupts	edn_intr	0.830s	27.812us	1	1	100.00
V2	alerts	edn_alert	1.120s	219.707us	1	1	100.00
V2	errs	edn_err	1.040s	41.241us	1	1	100.00
V2	disable	edn_disable	0.800s	13.376us	1	1	100.00
		edn_disable_auto_req_mode	1.260s	36.787us	1	1	100.00
V2	stress_all	edn_stress_all	1.790s	537.182us	1	1	100.00
V2	intr_test	edn_intr_test	0.820s	15.679us	1	1	100.00
V2	alert_test	edn_alert_test	0.940s	21.002us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.630s	108.140us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.630s	108.140us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.850s	51.463us	1	1	100.00
		edn_csr_rw	0.870s	31.893us	1	1	100.00
		edn_csr_aliasing	1.470s	62.464us	1	1	100.00
		edn_same_csr_outstanding	0.860s	33.775us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.850s	51.463us	1	1	100.00
		edn_csr_rw	0.870s	31.893us	1	1	100.00
		edn_csr_aliasing	1.470s	62.464us	1	1	100.00
		edn_same_csr_outstanding	0.860s	33.775us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.550s	400.276us	1	1	100.00
		edn_tl_intg_err	1.430s	79.874us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.890s	18.239us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.120s	219.707us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.550s	400.276us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.550s	400.276us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.550s	400.276us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.550s	400.276us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.120s	219.707us	1	1	100.00
		edn_sec_cm	4.550s	400.276us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.120s	219.707us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.430s	79.874us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.165m	7.394ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00