HMAC Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.650s 2.863ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.650s 70.115us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.760s 25.684us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.360s 319.063us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.070s 233.289us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.610s 25.626us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.760s 25.684us 1 1 100.00
hmac_csr_aliasing 2.070s 233.289us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 43.430s 1.111ms 1 1 100.00
V2 back_pressure hmac_back_pressure 44.820s 1.240ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.540s 739.563us 1 1 100.00
hmac_test_sha384_vectors 18.440s 516.807us 1 1 100.00
hmac_test_sha512_vectors 18.140s 226.719us 1 1 100.00
hmac_test_hmac256_vectors 5.140s 741.991us 1 1 100.00
hmac_test_hmac384_vectors 6.510s 229.833us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 947.344us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.490s 922.792us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.506m 2.703ms 1 1 100.00
V2 error hmac_error 17.660s 1.951ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.415m 10.641ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.650s 2.863ms 1 1 100.00
hmac_long_msg 43.430s 1.111ms 1 1 100.00
hmac_back_pressure 44.820s 1.240ms 1 1 100.00
hmac_datapath_stress 5.506m 2.703ms 1 1 100.00
hmac_burst_wr 8.490s 922.792us 1 1 100.00
hmac_stress_all 24.680m 149.044ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.650s 2.863ms 1 1 100.00
hmac_long_msg 43.430s 1.111ms 1 1 100.00
hmac_back_pressure 44.820s 1.240ms 1 1 100.00
hmac_datapath_stress 5.506m 2.703ms 1 1 100.00
hmac_wipe_secret 1.415m 10.641ms 1 1 100.00
hmac_test_sha256_vectors 7.540s 739.563us 1 1 100.00
hmac_test_sha384_vectors 18.440s 516.807us 1 1 100.00
hmac_test_sha512_vectors 18.140s 226.719us 1 1 100.00
hmac_test_hmac256_vectors 5.140s 741.991us 1 1 100.00
hmac_test_hmac384_vectors 6.510s 229.833us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 947.344us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.650s 2.863ms 1 1 100.00
hmac_long_msg 43.430s 1.111ms 1 1 100.00
hmac_back_pressure 44.820s 1.240ms 1 1 100.00
hmac_datapath_stress 5.506m 2.703ms 1 1 100.00
hmac_burst_wr 8.490s 922.792us 1 1 100.00
hmac_error 17.660s 1.951ms 1 1 100.00
hmac_wipe_secret 1.415m 10.641ms 1 1 100.00
hmac_test_sha256_vectors 7.540s 739.563us 1 1 100.00
hmac_test_sha384_vectors 18.440s 516.807us 1 1 100.00
hmac_test_sha512_vectors 18.140s 226.719us 1 1 100.00
hmac_test_hmac256_vectors 5.140s 741.991us 1 1 100.00
hmac_test_hmac384_vectors 6.510s 229.833us 1 1 100.00
hmac_test_hmac512_vectors 8.060s 947.344us 1 1 100.00
hmac_stress_all 24.680m 149.044ms 1 1 100.00
V2 stress_all hmac_stress_all 24.680m 149.044ms 1 1 100.00
V2 alert_test hmac_alert_test 0.620s 12.255us 1 1 100.00
V2 intr_test hmac_intr_test 0.570s 61.780us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.950s 298.404us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.950s 298.404us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.650s 70.115us 1 1 100.00
hmac_csr_rw 0.760s 25.684us 1 1 100.00
hmac_csr_aliasing 2.070s 233.289us 1 1 100.00
hmac_same_csr_outstanding 1.300s 350.309us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.650s 70.115us 1 1 100.00
hmac_csr_rw 0.760s 25.684us 1 1 100.00
hmac_csr_aliasing 2.070s 233.289us 1 1 100.00
hmac_same_csr_outstanding 1.300s 350.309us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.870s 376.724us 1 1 100.00
hmac_tl_intg_err 1.460s 417.854us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.460s 417.854us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.650s 2.863ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.070s 112.725us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 34.140s 2.358ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.410s 89.894us 1 1 100.00
TOTAL 28 28 100.00