I2C Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.108m	2.012ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	24.850s	1.193ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.660s	19.829us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.800s	41.707us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.440s	915.481us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.100s	256.011us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.770s	28.816us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.800s	41.707us	1	1	100.00
		i2c_csr_aliasing	1.100s	256.011us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.760s	34.647us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	17.721m	117.668ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	4.400m	12.322ms	1	1	100.00
V2	host_override	i2c_host_override	0.640s	19.555us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	41.960s	10.814ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	53.900s	2.847ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.820s	174.842us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.920s	838.928us	1	1	100.00
		i2c_host_fifo_reset_rx	3.650s	201.716us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.468m	2.664ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	16.400s	2.308ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.730s	180.360us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.670s	497.528us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	29.611m	70.715ms	0	1	0.00
V2	target_maxperf	i2c_target_perf	2.990s	4.319ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	27.160s	1.870ms	1	1	100.00
		i2c_target_intr_smoke	5.750s	1.498ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.110s	301.719us	1	1	100.00
		i2c_target_fifo_reset_tx	1.290s	213.878us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.288m	50.687ms	1	1	100.00
		i2c_target_stress_rd	27.160s	1.870ms	1	1	100.00
		i2c_target_intr_stress_wr	31.160s	29.090ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.230s	2.772ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	7.570s	10.024ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	2.210s	1.980ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.930s	677.090us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.160s	531.668us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.370s	159.910us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.400m	12.322ms	1	1	100.00
		i2c_host_perf_precise	11.350s	2.975ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	16.400s	2.308ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.000s	48.696us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.870s	921.480us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.850s	578.191us	1	1	100.00
		i2c_target_nack_txstretch	1.340s	640.422us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.170s	3.109ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.900s	1.994ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.850s	51.726us	1	1	100.00
V2	intr_test	i2c_intr_test	0.620s	71.553us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.880s	248.065us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.880s	248.065us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.660s	19.829us	1	1	100.00
		i2c_csr_rw	0.800s	41.707us	1	1	100.00
		i2c_csr_aliasing	1.100s	256.011us	1	1	100.00
		i2c_same_csr_outstanding	1.070s	62.663us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.660s	19.829us	1	1	100.00
		i2c_csr_rw	0.800s	41.707us	1	1	100.00
		i2c_csr_aliasing	1.100s	256.011us	1	1	100.00
		i2c_same_csr_outstanding	1.070s	62.663us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.200s	86.669us	1	1	100.00
		i2c_sec_cm	0.820s	44.336us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.200s	86.669us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.590s	353.725us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.660s	507.346us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.890s	1.574ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.107061180200795278353892565225958723361702442855569952311773949248985590215242
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  34646542 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  34646542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.50012151170936405032708292691351710592457049536969985872606206449657847621315
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1573534006 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1573534006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.84258908561755098076012676792326157197634017650919057960586705248980059181087
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 497527595 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 497527595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:

  • Test i2c_target_stretch has 1 failures.

    • 0.i2c_target_stretch.31588171500165984778272289976842994285081872669510261916096635637621673530302
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log

        UVM_FATAL @ 10024121040 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
        UVM_INFO @ 10024121040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.67903670383773133841154565635140008003317933841006077559801573825103295922462
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 507345713 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 66 [0x42])
        UVM_INFO @ 507345713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:

  • Test i2c_target_stress_all has 1 failures.

    • 0.i2c_target_stress_all.2864529692279960258985931300995751702579965166824817610368876000754959334511
      Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

        UVM_FATAL @ 70715078452 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
        UVM_INFO @ 70715078452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.99534857894810114909980331023067621496671251483199325629773785281154570292883
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 353724984 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 353724984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.104655211128943304698556949420342129283696809517567468773982888465703014520952
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 180359769 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xf860ef14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 180359769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.84005887503135236994584944408348708588638389342568622410982158504354470429005
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 640421922 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 640421922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---