KEYMGR Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.540s	42.822us	1	1	100.00
V1	random	keymgr_random	10.010s	763.537us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.940s	38.110us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.010s	96.321us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	7.630s	377.411us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.580s	233.482us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.190s	46.947us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.010s	96.321us	1	1	100.00
		keymgr_csr_aliasing	3.580s	233.482us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.130s	1.832ms	1	1	100.00
V2	sideload	keymgr_sideload	2.160s	953.295us	1	1	100.00
		keymgr_sideload_kmac	4.490s	194.235us	1	1	100.00
		keymgr_sideload_aes	1.820s	136.492us	1	1	100.00
		keymgr_sideload_otbn	1.710s	36.686us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.190s	213.048us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.530s	107.642us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.290s	547.508us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.030s	45.007us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.800s	63.815us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.610s	54.848us	1	1	100.00
V2	stress_all	keymgr_stress_all	23.210s	1.917ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.670s	25.198us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.690s	13.107us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.400s	62.934us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.400s	62.934us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.940s	38.110us	1	1	100.00
		keymgr_csr_rw	1.010s	96.321us	1	1	100.00
		keymgr_csr_aliasing	3.580s	233.482us	1	1	100.00
		keymgr_same_csr_outstanding	1.680s	199.687us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.940s	38.110us	1	1	100.00
		keymgr_csr_rw	1.010s	96.321us	1	1	100.00
		keymgr_csr_aliasing	3.580s	233.482us	1	1	100.00
		keymgr_same_csr_outstanding	1.680s	199.687us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
		keymgr_tl_intg_err	3.520s	113.271us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.580s	754.805us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.580s	754.805us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.580s	754.805us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.580s	754.805us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	3.050s	128.629us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.520s	113.271us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.580s	754.805us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.130s	1.832ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	10.010s	763.537us	1	1	100.00
		keymgr_csr_rw	1.010s	96.321us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	10.010s	763.537us	1	1	100.00
		keymgr_csr_rw	1.010s	96.321us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	10.010s	763.537us	1	1	100.00
		keymgr_csr_rw	1.010s	96.321us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.530s	107.642us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.800s	63.815us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.800s	63.815us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	10.010s	763.537us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	6.950s	477.747us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.300s	366.643us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.530s	107.642us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.300s	366.643us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.300s	366.643us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.300s	366.643us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.300s	437.672us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.300s	366.643us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.530s	376.629us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	30	100.00