KMAC/UNMASKED Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	45.190s	8.083ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.000s	22.770us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.020s	28.910us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.670s	506.378us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.140s	1.098ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.330s	303.117us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.020s	28.910us	1	1	100.00
		kmac_csr_aliasing	4.140s	1.098ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.880s	13.815us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.270s	66.334us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.832m	117.257ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.276m	24.511ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.020m	123.971ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.842m	57.261ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.410s	3.464ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.961m	125.488ms	1	1	100.00
		kmac_test_vectors_shake_128	30.856m	131.743ms	1	1	100.00
		kmac_test_vectors_shake_256	4.270m	20.246ms	1	1	100.00
		kmac_test_vectors_kmac	1.490s	78.893us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.180s	114.329us	1	1	100.00
V2	sideload	kmac_sideload	5.000m	79.994ms	1	1	100.00
V2	app	kmac_app	10.850s	6.711ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.768m	48.487ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.270s	887.493us	1	1	100.00
V2	error	kmac_error	1.613m	1.835ms	1	1	100.00
V2	key_error	kmac_key_error	3.690s	1.304ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	46.930s	10.148ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.170s	261.396us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	17.650s	1.237ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.260s	392.193us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.360s	98.731us	1	1	100.00
V2	stress_all	kmac_stress_all	6.438m	114.238ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.760s	38.668us	1	1	100.00
V2	alert_test	kmac_alert_test	0.970s	27.309us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.660s	102.732us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.660s	102.732us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.000s	22.770us	1	1	100.00
		kmac_csr_rw	1.020s	28.910us	1	1	100.00
		kmac_csr_aliasing	4.140s	1.098ms	1	1	100.00
		kmac_same_csr_outstanding	1.690s	63.473us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.000s	22.770us	1	1	100.00
		kmac_csr_rw	1.020s	28.910us	1	1	100.00
		kmac_csr_aliasing	4.140s	1.098ms	1	1	100.00
		kmac_same_csr_outstanding	1.690s	63.473us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.830s	350.382us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.830s	350.382us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.830s	350.382us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.830s	350.382us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.750s	803.947us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	48.790s	9.447ms	1	1	100.00
		kmac_tl_intg_err	3.100s	469.236us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.100s	469.236us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.360s	98.731us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	45.190s	8.083ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.000m	79.994ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.830s	350.382us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.790s	9.447ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.790s	9.447ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.790s	9.447ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	45.190s	8.083ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.360s	98.731us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.790s	9.447ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	15.130s	812.581us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	45.190s	8.083ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.380s	2.404ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.82006819965251249930461981350557969937021845343407462295557327750421574132250
      Line 83, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10148298392 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xecdaf000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
        UVM_INFO @ 10148298392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.81678759144945412271639238695044328485834266516467241920939985408867960487861
      Line 159, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2403733273 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2403733273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---