MBX Simulation Results

Wednesday September 24 2025 16:10:09 UTC

GitHub Revision: f250b50

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.367m	22.374ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	16.067us	1	1	100.00
V1	csr_rw	mbx_csr_rw	1.000s	33.954us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	3.000s	151.979us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	1.000s	24.257us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	45.509us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	1.000s	33.954us	1	1	100.00
		mbx_csr_aliasing	1.000s	24.257us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	7.000s	996.709us	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	2.000s	20.908us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	2.000s	62.297us	0	1	0.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	18.000s	2.221ms	1	1	100.00
V2	alert_test	mbx_alert_test	1.000s	19.268us	1	1	100.00
V2	intr_test	mbx_intr_test	1.000s	26.365us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	3.000s	91.002us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	3.000s	91.002us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	16.067us	1	1	100.00
		mbx_csr_rw	1.000s	33.954us	1	1	100.00
		mbx_csr_aliasing	1.000s	24.257us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	32.783us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	16.067us	1	1	100.00
		mbx_csr_rw	1.000s	33.954us	1	1	100.00
		mbx_csr_aliasing	1.000s	24.257us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	32.783us	1	1	100.00
V2		TOTAL			5	8	62.50
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	285.608us	1	1	100.00
		mbx_sec_cm	1.000s	17.059us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			13	16	81.25

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 3 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.79255010890444679875496449096271488898261352437935494567741172638614143985133
      Line 236, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @ 996708745 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 996708745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.51309963766923216633502091402502095535774202196500745269627326899182810717001
      Line 173, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @  20907588 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  20907588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.85937562561985577620759096536370275157793998505636288593008313196054758455423
      Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @  62296845 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  62296845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---